M41ST87W datasheet(17/54 Pages) STMICROELECTRONICS

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M41ST87W

Operating modes

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2.3

WRITE mode

In this mode the master transmitter transmits to the M41ST87Y/W slave receiver. Bus

protocol is shown in Figure 12: "WRITE mode sequence". Following the START condition

and slave address, a logic '0' (R/W̅ = 0) is placed on the bus and indicates to the

addressed device that word address An will follow and is to be written to the on-chip

address pointer. The data word to be written to the memory is strobed in next and the

internal address pointer is incremented to the next memory location within the RAM on the

reception of an acknowledge clock. The M41ST87Y/W slave receiver will send an

acknowledge clock to the master transmitter after it has received the slave address (see

Figure 9: "Slave address location") and again after it has received the word address and

each data byte.

Figure 12: WRITE mode sequence

Figure 13: WRITE cycle timing: RTC and external SRAM control signals

Available in SOX28 package only.

2.4

Data retention mode

With valid VCC applied, the M41ST87Y/W can be accessed as described above with READ

or WRITE cycles. Should the supply voltage decay, the M41ST87Y/W will automatically

deselect, write protecting itself (and any external SRAM) when VCC falls between VPFD

(max) and VPFD (min) (see Figure 28: "Power down/up mode AC waveforms", Table 21:

"Power down/up AC characteristics"). This is accomplished by internally inhibiting access

to the clock registers. At this time, the reset pin (

RST)isdrivenactiveandwillremainactive

until VCC returns to nominal levels. External RAM access is inhibited in a similar manner by

forcing E̅

CON to a high level. This level is within 0.2 volts of the VBAT

. E̅

CON will remain at this

level as long as VCC remains at an out-of-tolerance condition. When VCC falls below the

battery backup switchover voltage (VSO), power input is switched from the VCC pin to the

battery, and the clock registers and external SRAM are maintained from the attached

battery supply.

All signal outputs become high impedance. The VOUT pin is capable of supplying 100 µA of

current to the attached memory with less than 0.3 volts drop under this condition. On power

up, when VCC returns to a nominal value, write protection continues for trec by inhibiting

BUS ACTIVIT Y:

SD A LINE

BUS ACTIVIT Y:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SL AVE

ADDRESS

(1)

ECON

(1)

t EXPD

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