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M41ST87WMX6F 数据表(PDF) 36 Page - STMicroelectronics

部件名 M41ST87WMX6F
功能描述  5.0 and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM
PDF  54 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M41ST87WMX6F 数据表(HTML) 36 Page - STMicroelectronics

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Clock operation
M41ST87W
36/54
DocID9497 Rev 11
3.7
Full-time 32 kHz square wave output
The M41ST87Y/W offers the user a special 32 kHz square wave function which defaults to
output on the F32k pin (pin 21) as long as VCC
≥ V
SO, and the oscillator is running
(ST bit = '0'). This function is available within one second (typ) of initial power-up and can
only be disabled by setting the 32 kE bit to '0' or the ST bit to '1.' If not used, the F32k pin
should be disconnected and allowed to float.
Note: The F32k pin is an open drain which requires an external pull-up resistor.
3.8
Power-on reset
The M41ST87Y/W continuously monitors VCC. When VCC falls to the power fail detect trip
point, the
RSTpullslow(opendrain)andremainslowonpower-upfort
rec after VCC passes
VPFD(max). The
RSTpinisanopendrainoutputandanappropriatepull-upresistorshould
be chosen to control rise time.
Note: A power-on reset will result in resetting the following control bits to '0': OFIE, AFE,
ABE, SQWE, FT, WDS, BMB0-BMB4, RB0, RB1, TIE1, and TIE2 (see ).
3.9
Reset inputs (
������������������������������������������������������������������������and������������������������������������������������������������������������)
The M41ST87Y/W provides two independent inputs which can generate an output reset.
The function of these resets is identical to a reset generated by a power cycle. Table 11:
"Reset AC characteristics" and Figure 26: "RSTIN1 and RSTIN2 timing waveforms"
illustrate the AC reset characteristics of this function. Pulses shorter than tR1 and tR2 will not
generate a reset condition.
RSTIN1andRSTIN2areeachinternallypulleduptoV
CC
through a 100 kΩ resistor. Note that
RSTIN1triggersonthefallingedgewhileRSTIN2
triggers on the rising edge.
Note:
������������������������������������������������������������2isavailableonlyintheSOX28package.
Figure 26:
������������������������������������������������������������������������and������������������������������������������������������������������������timingwaveforms
RSTIN1
RST
RSTIN2
tR1
trec
Hi-Z
tR2
trec
Hi-Z



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