DocID031629 Rev 1

15/27

PM8804

Applications information

27

As for delay time, a resistor must always be connected to BLK pin, otherwise the device

operation will be stopped. Values for DT and BLK must be selected to be compatible with

the selected switching frequency; this constraint becomes more critical for high switching

frequencies due to the reduced duration of pulses.

The following relation con be used as a general “rule of thumb”:

Equation 3

2 · DT + BLK ≤ 10% · TSW

In case of FSW = 500 KHz, TSW is 2 µs and assuming a duty cycle of 50%, the clock pulse

lasts 1 µs. In order to satisfy Equation 3, two possible combination of DT and BLK are:

1.

DT = 30 ns, BLK = 30 ns

2.

DT = 20 ns, BLK = 50 ns

5.4

Soft-start / soft-stop and SS pin

The soft-start feature allows the output voltage to ramp-up in a safe and controlled way.

At the startup of the converter, the input voltage of the PWM comparator (CTL pin) is

clamped to the SS pin voltage, which is progressively ramped-up until it reaches the

regulation voltage. This results in a converter duty cycle increasing from zero to the

operative value.

The voltage ramp on SS pin is achieved by charging an external CSS capacitor connected

to the pin with a 2 µA internal current source.

Taking into account that the output voltage will start to rise only when the CTL voltage is

higher than 0.7 V, the effective duration of the output voltage soft-start ramp can be

estimated with the following formula:

Equation 4

The CTL voltage level depends on many factors: the topology, the converter working mode

and the output capacitance. Typical values are in the range from 1 to 2 V. Assuming a mean

value of CTL = 1.5 V and considering CSS = 33 nF, the resulting soft-start time will be about

13 mS.

Typical values for CSS are in the range 10 nF to 100 nF.

At the start-up, the baseline of 0.7 V on CTL is reached charging the soft-start capacitor with

a 10

A current source. After the start-up phase, the SS voltage level is actively maintained

at 2.3 V by an internal control circuitry, which also manages overcurrent and fault conditions.

In case of normal shutdown or thermal fault, the device features a soft-stop procedure. The

soft-stop helps to reduce the stress and the overvoltages on the power MOSFET and it is

achieved discharging slowly the soft-start capacitor with a 10

A current sink.

Except for thermal protection, the soft-stop is not applied for all the other fault conditions.

A summary is reported in Table 6. The soft-stop can be disabled connecting the MODE pin

to AGND.

tSS ms



CSS nF

 CTL V

 0.7 V



–



2

A



-------------------------------------------------



=