Applications information

PM8804

16/27

DocID031629 Rev 1

5.5

PWM comparator / slope compensation and CTL pin

In a typical isolated topology, the error amplifier is located outside the IC and the feedback

signal is taken on the collector of an optocoupler, while the current is sensed through a

sense resistor Rs connected between the source of the primary side MOSFET and the

PGND pin.

The PWM comparator produces the PWM duty cycle by comparing the Rs ramp signal on

CS with the error voltage derived from the error amplifier output.

The CTL voltage is internally pulled up to a fixed reference of 3.3 V using an internal 3.3 K



resistor, and it is reduced by a 4:1 divider before being connected to the PWM comparator

input.

The PWM duty cycle increases with the voltage at the CTL pin. The controller output duty

cycle reduces to zero when the CTL pin voltage drops below approximately 0.7 V.

For duty cycles greater than 50%, current mode control loops are subject to sub-harmonic

oscillation.

The device fixes the maximum duty cycle at 80% and implements a slope compensation

technique consisting in adding a fixed slope voltage ramp to the signal at the CS pin. This is

achieved by injecting a 21.5 µA saw tooth current into the current sense signal path on an

integrated 2 k

 series resistor.

Additional slope compensation may be added by increasing the source impedance of the

cur-rent sense signal connecting a resistor between the CS pin and the source of the

current sense signal. The net effect is to further increase the slope of the voltage ramp at the

PWM comparator terminals.

5.6

Current limit and CS pin

The current sensed through the CS pin is compared to two fixed levels of 250 mV and

350 mV.

The lower level of 250 mV is used to perform a cycle-by-cycle current limit, terminating the

PWM pulse. In case of recurring overload a timing structure is activated through SS pin,

sourcing a small current of about 2 µA on SS capacitor. The voltage on SS rises whenever

during a PWM cycle an overcurrent event occurs, while decreases to the default voltage

(2.3 V) if it does not.

Table 6. Fault management

Faults

Reaction

Turn off type

OV on VC

4 attempts then latched off state

Fast turn off

OC2

4 attempts then latched off state

Fast turn off

Overtemperature

The device attempts a new soft-start only when the OT

condition is removed

Soft-stop

UV on VC

The device attempts a new soft-start only when the VCUV rising

threshold is passed again

Fast turn off