DocID031629 Rev 1

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PM8804

Pins description and configuration

27

10

PGND

System power and analog ground. Power ground for the gate drivers.

This pin will be connected to AGND in a star ground configuration: a single connection point

close to the pin 10. See more details in Section 6: Layout guidelines on page 21.

11

GAT2

Secondary gate driver output.

AUX gate driver output for active clamp or synchronous rectification designs. 1 A peak sink -

0.8 A source current capability (5

 typ. MOSFETs). Its time delay with respect to GAT1 signal

can be adjusted through DT pin. The operation of GAT2 pin can be selected through MODE

pin.

12

VC

Output of the internal high-voltage start up regulator.

When the voltage applied to VIN is powered up, the startup regulator charges the external

capacitance up to 8 V typ. and a converter startup is attempted; Filter this pin with a ceramic

capacitor connected to AGND; a 2.2

F, 25 V ceramic capacitor is typically enough to cover

most of the applications.

13

MODE

Operation mode set.

Through this pin it is possible to select operation mode for the converter.

Connect this pin to AGND to turn off GAT2 when not used, and to disable the soft-stop feature.

If left open, this pin is internally pulled up: GAT2 and soft-stop features are enabled.

14

CS

Current sense input for current mode control and overcurrent protection.

Current sensing is accomplished using a dedicated current sense comparator. If the CS pin

voltage exceeds 0.25 V, the GAT1 pin switches low for cycle-by-cycle current limiting. CS is

internally held low for a blanking period after GAT1 switches high to blank leading edge current

spikes.

15

CTL

The input of the pulse width modulator (PWM) circuit.

CTL useful range is between 0.7 V and 1.7 V and a pull-up resistance of 3.3 k

 is integrated;

this resistance may also be used to bias an optocoupler transistor in isolated applications.

16

BLK

Blanking time set.

An internal blanking time is integrated in order to prevent false overcurrent detection to

terminate the PWM waveform. This is done after the rising edge of the primary side MOSFET.

The masking time, active for a duration between 10 ns and 200 ns is set by a resistor placed

between BLK and AGND.

-

EP

Exposed pad.

Connect this pad to a PCB copper plane to improve heat dissipation; it must be electrically

connected to AGND.

Table 2. Pin description (continued)

Pin no.

Name

Function