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PM8804TR 数据表(PDF) 12 Page - STMicroelectronics |
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PM8804TR 数据表(HTML) 12 Page - STMicroelectronics |
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12 / 27 page ![]() Applications information PM8804 12/27 DocID031629 Rev 1 5 Applications information 5.1 High-voltage start-up regulator and VC pin The device embeds a high-voltage startup regulator to provide the supply voltage to the internal current mode PWM controller during its startup phase and if needed, also during the normal operation. The regulated voltage is typically 8 V and it is internally connected to the VC pin as well as to the controller section. In normal isolated topology, the VC pin is diode-connected to the auxiliary winding of the transformer used for the flyback or forward configuration. When the voltage from the transformer exceeds the regulated voltage, the high-voltage regulator is shut off, reducing the amount of power dissipated inside the PM8804. More in detail, when the auxiliary voltage surpasses 8.3 V, the HV regulator resets its regulation level to less than 6.0 V. In this way, a loosely regulated voltage from the external auxiliary supply is allowed without current-sharing with the internal regulator. If the auxiliary voltage drops under 6 V, the internal regulator is turned on in order to supply the controller and maintain the output regulation. While the auxiliary voltage has to be higher than 8.0 V to take advantage of the auxiliary winding, it must be also lower than 15.3 V for all operating conditions, to avoid the intervention of the internal OV protection. A ceramic capacitor at least 2.2 F must be connected at the controller output to guarantee the stability of the HV regulator. For applications with high current drawn from VC pin, a large capacitance should be connected on VC pin in order to avoid converter switch-off during the startup phase. A UV/OV mechanism monitors the level of voltage on the VC pin. When VC voltage overcomes the UVLO rising threshold (VCUV_R), the PWM controller is enabled by the assertion of PGD signal and it remains enabled until the VC voltage drops below the UVLO falling threshold (VCUV_F) or the PGD is de-asserted. The VCUV_F is set to 5.0 V typically: below this voltage the PWM controller operations are stopped and the outputs frozen in default state. The overvoltage circuitry detects a feedback fault condition on the output voltage by sensing the VC voltage. If VC exceeds the OV rising threshold (VCOV_R), the PWM controller is stopped, the soft-start capacitor discharged, then a new start up is attempted. In case of persistent overvoltage, the control logic tries 4 cycles of fast hiccup before definitively shutting down the PWM controller. To restart the device the main supply VIN must be lowered to ground and then powered up again. The HV regulator internal current limit is set at 22 mA typ. This value includes the current internally drawn to bias the controller, the gate drivers, and the external components that may be connected to the VC pin. The use of an external auxiliary source is strongly recommended: the amount of power dissipated inside the device will be significantly reduced. |
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