UCD3138 datasheet(28/99 Pages) TI2

28 / 99 page

The registers and bit definitions inside the system and peripheral blocks are detailed in the programmer’s guide

for each peripheral.

9.3.2 Boot ROM

The UCD3138 incorporates a 4k boot ROM. This boot ROM includes support for:

• Program download through the PMBus

• Device initialization

• Examining and modifying registers and memory

• Verifying and executing program FLASH automatically

• Jumping to a customer defined boot program

The Boot ROM is entered automatically on device reset. It initializes the device and then performs checksums on

the Program FLASH. If the first 2 kB of program FLASH has a valid checksum, the program jumps to location 0

in the Program FLASH. This permits the use of a customer boot program. If the first checksum fails, it performs a

checksum on the complete 32 kB of program flash. If this is valid, it also jumps to location 0 in the program flash.

This permits full automated program memory checking, when there is no need for a custom boot program.

If neither checksum is valid, the Boot ROM stays in control, and accepts commands via the PMBus interface

These functions can be used to read and write to all memory locations in the UCD3138. Typically they are used

to download a program to Program Flash, and to command its execution

9.3.3 Customer Boot Program

As described above, it is possible to generate a user boot program using 2 kB or more of the program flash. This

can support things which the Boot ROM does not support, including:

• Program download via UART – useful especially for applications where the UCD3138 is isolated from the

host (for example, PFC)

• Encrypted download – useful for code security in field updates.

9.3.4 Flash Management

The UCD3138 offers a variety of features providing for easy prototyping and easy flash programming. At the

same time, high levels of security are possible for production code, even with field updates. Standard firmware

will be provided for storing multiple copies of system parameters in data flash. This is minimizes the risk of losing

information if programming is interrupted.

9.4 System Module

The System Module contains the interface logic and configuration registers to control and configure all the

memory, peripherals and interrupt mechanisms. The blocks inside the system module are the address decoder,

memory management controller, system management unit, central interrupt unit, and clock control unit.

9.4.1 Address Decoder (DEC)

The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory map

addresses are selectable through configurable register settings. These memory selects can be configured from

1 kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM execution, which is

then configured by the ROM code to the application setup. During access to the DEC registers, a wait state is

asserted to the CPU. DEC registers are only writable in the ARM privilege mode for user mode protection.

9.4.2 Memory Management Controller (MMC)

The MMC manages the interface to the peripherals by controlling the interface bus for extending the read and

write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of address space

decoding.

UCD3138

SLUSAP2J – MARCH 2012 – REVISED NOVEMBER 2021

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