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UCD3138 数据表(PDF) 32 Page - Texas Instruments |
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UCD3138 数据表(HTML) 32 Page - Texas Instruments |
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32 / 99 page  QT1 QB1 Lr ISOLATED GATE Transformer SYNCHRONOUS GATE DRIVE PRIM CURRENT VOUT +12V T1 T1 ORING CTL VA VBUS QT2 QB2 D1 D2 T2 L1 Q5 RL C1 C2 R2 Q6 Q7 I_SHARE Vout Iout I_pri temp Vin VA ARM7 FAULT 0 AD01 AD02/CMP0 AD 03/CMP1/CMP2 AD04/CMP3 AD05/CMP4 AD00 AD06/CMP5 FAULT 1 FAULT 2 GPIO2 GPIO3 GPIO1 AD07/CMP6 AD08 AD09 DPWM0B DPWM1B DPWM2A DPWM2B ORING_CRTL P_GOOD DPWM3A DPWM3B Vout ON/OFF FAILURE ACFAIL_OUT ACFAIL_IN I_pri Iout EADC0 EADC1 CLA0 CLA1 EADC2 DPWM0 DPWM1 DPWM2 DPWM3 Duty for mode switching Vref Load Current PCM CBC < CPCC PMBus UART 1 UART0 Primary OSC WD RST Memory FAULT Current Sensing I_pri Figure 9-2. Secondary-Referenced Phase-Shifted Full Bridge Control With Synchronous Rectification 9.5.2.2 LLC Example In LLC, three modes are used. At the highest frequency, a pulse width modulated mode (Multi Mode) is used. As the frequency decreases, resonant mode is used. As the frequency gets still lower, the synchronous MOSFET drive changes so that the on-time is fixed and does not increase. In addition, the LLC control supports cycle- by-cycle current limiting. This protection function operates by a comparator monitoring the maximum current during the DPWMA conduction time. Any time this current exceeds the programmable comparator reference the pulse is immediately terminated. Due to classic instability issues associated with half-bridge topologies it is also possible to force DPWMB to match the truncated pulse width of DPWMA. Here are the waveforms for the LLC: Q1B Q1T QSR1 QSR2 fs< fr fr fs> fr fs= fr_max PWM Mode LLC Mode Tr= 1/fr Tr= 1/fr I SEC(t) UCD3138 SLUSAP2J – MARCH 2012 – REVISED NOVEMBER 2021 www.ti.com 32 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD3138 |
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