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UCD3138 数据表(PDF) 3 Page - Texas Instruments |
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UCD3138 数据表(HTML) 3 Page - Texas Instruments |
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3 / 99 page  4 Functional Block Diagram Figure 4-1 shows a functional block diagram of the device. Front End 2 Analog Comparators Power and 1. 8 V Voltage Regulator AD07 AD06 AD04 V33DIO /RESET SCI_RX0 SCI_TX0 PMBUS_CLK PMBUS_DATA AGND V33D BP18 FAULT3 FAULT2 TCAP TMS TDI TDO TCK EXT_INT FAULT1 FAULT0 PWM1 PWM0 SCI_RX1 SCI_TX1 PMBUS_CTRL PMBUS_ALERT SYNC DGND DPWM3B DPWM3A DPWM2B DPWM2A DPWM1B DPWM1A DPWM0B DPWM0A EAP0 EAN0 EAP1 EAN1 V33A AD00 AD01 AD02 AD13 PID Based Filter 0 DPWM0 DPWM1 DPWM2 DPWM3 PID Based Filter 1 PID Based Filter 2 ADC_EXT_TRIG ADC12 ADC12 Control Sequencing , Averaging, Digital Compare, Dual Sample and hold AD[13:0] A B C D E F G Current Share Analog, Average, Master/Slave AD03 AD02 AD13 AGND PMBus Timers 4 – 16 bit (PWM) 1 – 24 bit UART0 UART1 GPIO Control JTAG Loop MUX ARM7TDMI-S 32 bit, 31. 25 MHz Memory PFLASH 32 kB DFLASH 2 kB RAM 4 kB ROM 4 kB Power On Reset Brown Out Detection Oscillator Internal Temperature Sensor Advanced Power Control Mode Switching, Burst Mode, IDE, Synchronous Rectification soft on & off Front End 1 Constant Power Constant Current Input Voltage Feed Forward Front End Averaging Digital Comparators Fault MUX & Control Cycle by Cycle Current Limit Digital Comparators DAC0 EADC X AFE Value Dither Σ CPCC Filter x Ramp SAR/Prebias Abs() Avg() 2 AFE 2 3-AFE Peak Current Mode Control Comparator A0 EAP2 EAN2 Front End 0 Figure 4-1. Functional Block Diagram Note Front-end 2 Recommended for Peak Current Mode Control www.ti.com UCD3138 SLUSAP2J – MARCH 2012 – REVISED NOVEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: UCD3138 |
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