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TLV9152SIRUGR 数据表(PDF) 34 Page - Texas Instruments |
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TLV9152SIRUGR 数据表(HTML) 34 Page - Texas Instruments |
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34 / 85 page  10.2 Layout Example + VIN VOUT RG RF Figure 10-1. Schematic Representation NC ±IN +IN V± V+ OUTPUT NC NC VS+ VS± GND Ground (GND) plane on another layer VOUT VIN GND Run the input traces as far away from the supply lines as possible RF RG Place components close to device and to each other to reduce parasitic errors Use low-ESR, ceramic bypass capacitor GND Use a low-ESR, ceramic bypass capacitor Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration TLV9151, TLV9152, TLV9154 SBOS986E – OCTOBER 2019 – REVISED JANUARY 2022 www.ti.com 34 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLV9151 TLV9152 TLV9154 |
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