ADA4356ABCZ datasheet(53/61 Pages) AD

53 / 61 page

Data Sheet

ADA4356

analog.com

Rev. 0

53 of 61

REG.

(HEX)

NAME

BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

DEFAULT

VALUE

(HEX)

COMMENTS

0x14

Output mode

Open

LVDS-

ANSI/

LVDS-

IEEE

option

0 =

LVDS-

ANSI,

1 =

LVDS-

IEEE

reduce

range

link

(global

see

Table

Open

Output

invert

(local)

Open

Output

format:

0 =

offset

binary,

1 =

two’s

comple

ment

(global)

0x01

Configures

the outputs

and format

of the data.

0x15

Output adjust

Open

Output driver

termination,

Bits[1:0]:

00 = none,

01 = 200Ω,

10 = 100Ω,

11 = 100Ω

Open

Output

drive:

0 = 1×

drive,

1 = 2×

drive

0x00

Determines

LVDS or

other

output

properties.

0x16

Output phase

Open

Input clock phase adjust,

Bits[6:4]

(value is the number of input

clock cycles of phase delay), see

Table 20

Output clock phase adjust, Bits[3:0]

(0000 through 1011), see Table 21

0x03

On devices

using global

clock divide,

0x16

determines

which phase

of the

divider

output is

used to

supply the

output

clock.

Internal

latching is

unaffected.

0x19

USER_PATT1_

LSB (global)

0x00

User-

defined

pattern

1LSB.

0x1A

USER_PATT1_

MSB (global)

B15

B14

B13

B12

B11

B10

0x00

User-

defined

pattern

1MSB.

0x1B

USER_PATT2_

LSB (global)

0x00

User-

defined

pattern

2LSB.

0x1C

USER_PATT2_

MSB (global)

B15

B14

B13

B12

B11

B10

0x00

User-

defined

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