Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance

changes. When a via must be used, increase the clearance size around it to minimize its capacitance.

Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up

interference from the other layers of the board. Be careful when designing test points, through-hole pins are not

recommended at high frequencies.

Figure 12-2 shows an example of a PCB layout with the TMUX1308 and TMUX1309. Some key considerations

are as follows:

• Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the

capacitor voltage rating is sufficient for the VDD supply.

• Keep the input lines as short as possible.

• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.

• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

12.2 Layout Example

N.C.

GND

A1

A2

S4

S6

D

S7

S5

EN

VDD

S2

S1

S0

S3

A0

TMUX130 8

Via to G ND plane

C

Wide (low inductance)

trace for power

N.C.

GND

A0

A1

S0B

S2B

DB

S3B

S1B

EN

VDD

S2A

S1A

DA

S0A

S3A

TMUX130 9

C

Wide (low inductance)

trace for power

Figure 12-2. TMUX1308 and TMUX1309 Layout Example

TMUX1308, TMUX1309

SCDS426E – MARCH 2020 – REVISED OCTOBER 2022

www.ti.com

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