ADMV8809ACCZ-R7 datasheet(5/54 Pages) AD

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Data Sheet

ADMV8809

SPECIFICATIONS

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TIMING SPECIFICATIONS

Table 2. Timing Specifications

Parameter

Min

Typ

Max

Unit

Test Conditions / Comments

RST low time to perform reset

SCLK cycle time (write)

SCLK cycle time (read)

2.5

SCLK high time

2.5

SCLK low time

CS falling edge to SCLK rising edge setup time

SCLK rising edge to hold time

Minimum CS high time for latching in data (for multiple SPI transactions)

CS rising edge to next SCLK rising edge ignore

SDI data setup time

t10

SDI data hold time

t11

SCLK falling edge to SDO valid (load capacitance (CL) = 10 pF)

t12

SDO rise and fall time (CL = 10 pF)

t13

CS rising edge to SDO tristate (CL = 10 pF)

t14

CS rising edge (end of SPI transaction) to lookup table (LUT) rising edge time (entering LUT control mode)

t15

LUT setup time LUT rising edge to CS rising edge (LUT control mode)

t16

LUT hold time CS rising edge to CS high (LUT control mode)

t17

2.5

CS high time (LUT control mode)

t18

2.5

CS low time (LUT control mode)

Timing Diagram

Figure 2. Timing Diagram

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