ADMV8809ACCZ-R7 datasheet(22/54 Pages) AD

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Data Sheet

ADMV8809

THEORY OF OPERATION

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or parallel pins), and select between LUTA or LUTB. Register 0x12

(LUT_CTL2) includes the LUT_INDEX_POINTER bits (Bits[4:0]),

which indicate the LUT entry used in SPI mode.

Users can select between two LUTs to use, LUTA and LUTB.

0x60 through Register 0x9F are for LUTB. Each LUT has 32 pairs

of the LUT_SW and LUT_FILTER registers.

Once users have configured the LUT register values, users can use

these LUT registers to configure the filter bands. Users can control

the LUT pointer by using either SPI mode or the parallel pins. If

using SPI mode, use Register 0x12 to control the LUT pointer.

If using the parallel pins, set the LUT_MODE bit to 1. Then, select

the LUT entry using the parallel pins. If the filter update timing is

required, set the LUT_LATCH bit to 1 to set it to latched mode,

where the LUT entry selected only updates on the next rising edge

of CS. Having this bit set to latched mode, the unused filter bands

will be set to HPF State 0 and LPF State 0, and these bands will

keep their current values, unless the values are overwritten by the

user.

If the LUT_LATCH bit is set to 0, it sets to combinational mode,

where the default values of the unused filter bands will be written

over. The filter bands default values are detailed in Register 0x00

through Register 0x03.

SWITCH SET

and output will be directed. Both switches (shown in Figure 1) are

paired to this register.

FILTER SETTINGS

and LPF states assigned on a filter band. Use the FILTER_SELECT

bits (Bits[7:6]) to select the filter band. The HPF bits (Bits[5:3])

and LPF bits (Bits[2:0]) hold the state value, which includes eight

configurable states. A value of 0 corresponds to setting the f3dB of

the filter to its lowest possible frequency. Conversely, a value of 7

corresponds to setting the f3dB of the filter to its highest possible

frequency.

READBACK REGISTERS

The ADMV8809 has dedicated readback registers. Register 0x15

(READBACK_SWITCH) and Register 0x16 through Register 0x19

(READBACK_FILTER1, READBACK_FILTER2, READBACK_FIL-

TER3, and READBACK_FILTER4). These registers represents the

actual settings of the switch, LPF, and HPF. See Register Summary

for further information.

FREQUENCY TERMINOLOGY

The 3dB bandwidth is a straightforward concept; however, because

the ADMV8809 is designed to operate over a wide frequency

range, there is frequency dependent insertion loss that results in

a negative slope vs. frequency. Additionally, depending upon the

selected filter and state, there may also be ripple within the pass

band. Given these characteristics, a variation is necessary to estab-

lish a reference frequency (fREF) from which the f3dB for each filter

can be computed. Analog Devices uses a consistent methodology

for determining the fREF and f3dB is to rely on the group delay

performance of a filter. The following is the methodology used for

determining the ADMV8809 specifications:

1. Find the peak group delay (GDPEAK) and peak group delay

frequency (fPEAK) as the filter insertion loss (S21) begins to roll

off.

2. For a LPF, divide fPEAK by 2 to find the average frequency

(fAVG). For a HPF, multiply fPEAK by 2. When fAVG is calculated,

determine the group delay at this frequency. Generally, the

group delay is flat and approximately equal to the average at

this particular frequency (fAVG).

3. Take the mathematical mean of the group delay from Step 1

and Step 2 to find the reference group delay (GDREF), and then

find the corresponding fREF and reference insertion loss (ILREF)

for this group delay.

4. Subtract 3dB from the ILREF to find the 3dB insertion loss

(IL3dB), and then find the corresponding f3dB.

CHIP RESET

Two methods are available to reset the ADMV8809 registers to their

default power-on state, a hard reset and a soft reset. The hard reset

uses the RST pin, and the soft reset utilizes Register 0x00.

To perform a hard reset, momentarily bring the RST pin low and

then high. See Figure 2 for the minimum required duration time for

the RST pin to be low.

To perform a soft reset, set Register 0x00 to 0x81. This action sets

the SOFTRESET and SOFTRESET_ bits high to initiate the reset.

The SOFTRESET and SOFTRESET_ bits are self resetting once

the reset operation completes.

Regardless of the reset method used, it is recommended to perform

the following after the chip resets:

►

Set Register 0x00 to 0x3C to enable the SDO pin and allow SPI

streaming with Endian ascending order.

►

Read back all registers on the chip.

ADMV8809ACCZ-R7 数据表(PDF) 22 Page - Analog Devices

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