pHAT Module Series

pHAT-RV Technical Description

pHAT-RV Technical Description

Page 20 of 27

3.7.6 I

2C Servo Control Register Format

Each servo control register consists of four control bits and a four bit speed control value

defined as follows:

Table 8: I

2C Servo Control Register Format

Bit

Bit value

Function

Description

A

128 (0x80)

Operate bit

When set activates the servo being

controlled

B

64 (0x40)

Reverse bit

When set reverses the position value for

the servo being controlled

C

32 (0x20)

SoftStart bit

When set on servo first activation, see

operate bit above, feeds position pulses to

the servo in a ramping manner until

position is attained

D

16 (0x10)

Speed bit

When set applies the speed value 0 to 15

SSSS

0 – 15 (0x00 –

0x0F)

Speed value

Speed value 0 to 15

3.7.7 I

2C Servo Status Register Format

Each servo status register consists of four status bits defined as follows:

Table 9: I

2C Servo Status Register Format

Bit

Bit value

Function

Description

A

128 (0x80)

Operation bit

Set when servo is operational

B

64 (0x40)

Reverse bit

Set when servo is in reverse operation

C

32 (0x20)

SoftStart bit

Set when SoftStart is in operation

D

16 (0x10)

Movement bit

Set when servo movement is in-progress

3.7.8 Servo Movement Complete Determination

Servo status register Bit (D) 16decimal are cleared to indicate if the current servo movement has

completed.

This indication is not derived from mechanical or electrical feedback from the servo being

controlled but is a function of the current servo speed selected and position.

When the slowest servo speed (0) is selected the determination of movement completion is

at its best. This is because the positional change of the servo between its current and final

position has been split into many sub-positions which must be attained before the final