pHAT Module Series

pHAT-RV Technical Description

pHAT-RV Technical Description

Page 25 of 27

6 References

6.1 I

2C protocols

Figure 2: I

2C Write protocol

1 1

1

0

A1 A0

0

GPM ADDRESS

REGISTER

ADDRESS

DATA

BYTE

Multiple bytes may be written before the ‘STOP’ condition. Data is written into registers

starting at ‘REGISTER ADDRESS’, then ‘REGISTER ADDRESS’ +1, then ‘REGISTER ADDRESS’ +2

etc.

Each byte transfer is acknowledged ‘ACK’ by the RV until the ‘STOP’ condition.

Figure 3: I

2C Read protocol

1 1

1

1

0

A1 A0

0

GPM ADDRESS

REGISTER

ADDRESS

DATA

BYTE 1

1 1 0

A1 A0

0

GPM ADDRESS

DATA

BYTE 2

‘DATA BYTE 1 & 2’ are register values returned from the RV. Each byte written is

acknowledged ‘ACK’ by the RV , every byte read is acknowledged ‘ACK’ by the I2C Master. A

Not-acknowledge ‘NACK’ condition is generated by the I2C Master when it has finished

reading.