ADC34RF72 datasheet(36/74 Pages) TI2

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7.3.5.5.2 Decimation Modes

There are 2 different decimation modes supported and all 8x DDCs must be configured to the same mode:

• Real decimation: The real input is low pass filtered and the filter output is down sampled by the decimation

factor (M). The output of the DDC block in this mode is a real signal and detailed DDC chain is shown in

Figure 7-23.

• Complex decimation with real input: The DDC is given a real input that is mixed with an NCO to produce a

complex output. The complex output is low pass filtered and down sampled by the decimation factor (M). The

output of the DDC block in this mode is a complex signal and detailed DDC chain is shown in Figure 7-25.

Each DDC has an enable control signal. If the DDC is disabled, the output is zero. The following blocks are part

of the DDC signal chain:

• Decimation: The possible decimation factors are B x 2N where the base factor B can be 1, 3 or 5 and N can

be a maximum of 15 for B = 1, 5 for B = 3 and 4 for B = 5.

When the base factor is 3 or 5, all the DDCs must share the same decimation factor setting. However,

when the base factor is 1 (decimations factors that are powers of 2), having an independent decimation

factors per DDC is possible since each DDC has a samples repeater block. When each DDC is configured

to a different decimation factor, the samples repeater for each DDC is adjusted so that all the DDC outputs

are rate matched to highest data rate DDC. For example, if two DDCs are active and one is configured in

decimation by 4 and the other in decimation by 16, the DDC configured for decimation by 16 automatically

gets rate matched to the decimation by 4 rate by repeating the samples by a factor of 4. Upon successful

configuration, the repeat factor can be readback for each DDC.

Note

Independent decimation factors are not supported when any DDC is configured for decimation by 2.

When decimation by 2 is used all other DDCs must be also be set to by 2.

Repeat Factor: The repeat factor is adjusted automatically for each DDC in cases where the effective JESD

line rate is below the lower threshold of 4Gbps. The repeat factor block is not available with base factors of 3

and 5.

• DDC_PFIR: The ADC32RF72 has an integrated programmable FIR filter block in the decimation chain where

the last stage filter is completely programmable. This feature is only available with decimation factors that are

powers of 2 (B = 1). The block is referred to as the DDC_PFIR. Each DDC_PFIR has up to 96 total taps

(across both inputs in complex decimation) with 17-bit resolution.

• DDC coarse gain (G): The fixed digital gain can be applied to each DDC path where the gain G is an

element of {0dB, 3dB, 6dB} and controllable for each DDC through the ddc_coarse_gain[7:0] signal.

• DDC_EQ: The DDC_EQ supports all the same modes the as the Digital DSP EQ.

Note

This EQ is not available for decimation factors of 2 and 3.

• DDC_COMPLEX_GAIN: Each DDC has a programmable complex gain. In real decimation mode, only the

real part of the gain is applied. The gain is in steps of 0.1dB from 0dB to 6dB; an independent gain setting is

available for the real and imaginary parts.

ddc_pfir_en[7:0]

ddc_in_real[7:0]

DDC_PFIR[7:0]

LAST

STAGE

MUX[7:0]

decimation_factor[7:0]

DDC_EQ[7:0]

DDC

MUX[7:0]

ddc_eq_en[7:0]

G ∈ {0dB, 3dB, 6dB}

ddc_coarse_gain[7:0]

ddc_out[7:0]

DDC_COMPLEX_GAIN

ddc_real_gain[7:0]

B*2

N-1

Figure 7-23. Real Decimation Signal Chain (decimation factors that are powers of 2 (B = 1))

ADC32RF72

SBASAL2 – NOVEMBER 2025

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