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ADC34RF72 数据表(PDF) 49 Page - Texas Instruments

部件名 ADC34RF72
功能描述  ADC32RF72 Dual Channel 1.5GSPS 16-bit RF Sampling ADC
PDF  74 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

ADC34RF72 数据表(HTML) 49 Page - Texas Instruments

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7.3.6.1.5 JESD204B/C Frame Assembly With Real Decimation
Table 7-21 lists the available JESD204B/C interface configurations and corresponding SerDes lane rates. The
boundary conditions are:
• JESD204B: lane rates from 4 (min) to 15Gbps (max)
• JESD204C: lane rates from 4 (min) to 24.75Gbps (max)
Examples of JESD204B/C frame assemblies are illustrated in Table 7-21 to Table 7-23.
Table 7-21. JESD Mode Options: Real Decimation
Output
Resolution
(bit)
L
M
F
S
JESD204B:
Lane Rate (Gbps)
JESD204B:
RATIO
[fSERDES/(FS/N)]
JESD204C:
Lane Rate (Gbps)
JESD204C:
RATIO
[fSERDES/(FS/N)]
16
4
2
1
1
FS x 20 x M / D / L
10
FS x 16 x 66 / 64 x
M / D / L
8.25
2
2
2
1
20
16.5
1
2
4
1
40
33
2
1
1
1
10
8.25
1
1
2
1
20
16.5
24
2
2
3
1
FS x 30 x M / D / L
30
FS x 24 x 66 / 64 x
M / D / L
24.75
1
2
6
1
60
49.5
1
1
3
1
30
24.75
D: Decimation setting
Table 7-22. Example JESD Frame Assembly: Real Decimation 16-bit output - Dual and Single Band
OUTPUT
LANE
LMFS =
4-2-1-1
LMFS =
2-2-2-1
LMFS =
1-2-4-1
LMFS =
2-1-1-1
LMFS =
1-1-2-1
STX0
A0 [15:8]
A0 [15:0]
A0 [15:0]
B0 [15:0]
A0 [15:8]
A0 [15:0]
STX1
A0 [7:0]
B0 [15:0]
A0 [7:0]
STX2
B0 [15:8]
STX3
B0 [7:0]
STX4..7
Table 7-23. Example JESD Sample Frame Assembly: Real Decimation 24-bit output - Dual and Single
Band
OUTPUT
LANE
LMFS =
2-2-3-1
LMFS =
1-2-6-1
LMFS =
1-1-3-1
STX0
A0 [23:0]
A0 [23:0]
B0 [23:0]
A0 [23:0]
STX1
B0 [23:0]
STX2..7
www.ti.com
ADC32RF72
SBASAL2 – NOVEMBER 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: ADC32RF72



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