ADL5571

Rev. 0 | Page 11 of 16

APPLICATIONS INFORMATION

BASIC CONNECTIONS

Figure 19 shows the basic connections for the ADL5571.

VCC1

RFIN

GND

VREG

RFOUT

NC

RFOUT

NC

5

6

7

8

15

16

14

13

ADL5571

C7

0.01µF

VPOS

VREG

C9

0.01µF

C2

2.2pF

C10

0.01µF

C8

0.01µF

STBY

C6

3.3pF

VPOS

C11

1µF

C5

OPEN

VPOS1

C12

1µF

C4

39pF

C3

2.7pF

VPOS1

VPOS

RFIN

RFOUT

W1

L3

2.7nH

L2

11nH

L1

1nH

NC = NO CONNECT

Figure 19. Basic Connections

Power Supply

The voltage supply on the ADL5571, which ranges from

3.2 V to 4.2 V, should be connected to the VCCx pins. VCC1 is

decoupled with Capacitor C7, whereas VCC2 uses a tank circuit

to prevent RF signals from propagating on the dc lines.

RF Input Interface

The RFIN pin is the port for the RF input signal to the power

amplifier. The L3 inductor, 2.7 nH, matches the input

impedance to 50 Ω.

RFIN

2.7nH

L3

6

Figure 20. RF Input with Matching Component

RF Output Interface

The parallel RF output ports have a shunt capacitor, C3 (2.7 pF),

and the line inductance of the microstrip line for optimized

output power and linearity. The characteristics of the ADL5571

are described for 50 Ω impedance after the output matching

capacitor (load after C3). C4 provides dc blocking on the

RF output.

RFOUT

RFOUT

C3

2.7pF

C4

39pF

L2

11nH

C5

OPEN

C12

1µF

RFOUT

VPOS1

15

14

Figure 21. RF Output

Transmit/Standby Enable

During normal transmit mode, the STBY pin is biased low

(0 V). However, during receive mode, the pin can be biased

high (2.5 V) to shift the device into standby mode, which

reduces current consumption to 9 mA.

VREG Enable

During normal transmit, the VREG pin is biased to 2.85 V and

draws 9 mA of current. When the VREG pin is low (0 V), the

device suspends itself into sleep mode (irrespective of supply

biasing). In this mode, the device draws less than 1 μA of

current.