L4990AD datasheet(10/24 Pages) STMICROELECTRONICS

10 / 24 page

The frequency can be established with the aid of

fig. 13 diagrams or considering the approximate

relationship:

fosc

≅

⋅ (0.693 ⋅ RT + KT)

(1)

where KT is defined as:

KT =







90, V15

= VREF

160 V15

= GND/OPEN

(2)

and is linked to the duration of the falling edge of

the sawtooth:

≅ 30 ⋅ 10-9 +KT ⋅ CT (3)

Td is also the duration of the sync pulses deliv-

ered at pin 1 and defines the upper extreme of

the duty cycle range, Dx (see pin 15 for Dx defini-

tion and calculation).

In case V15 is connected to VREF, however, the

switching freque ncy of the system will be as

high as half fosc.

If the IC is to be synchronized to an external oscil-

lator, RT and CT should be selected for a fosc

lower than the master frequency in any condition

(typically, 10-20% ), depending on the tolerance

of RT and CT itself.

Pin 3. DC (Duty Cycle Control). By biasing this

pin with a voltage between 1 and 3 V it is possible

to set the maximum duty cycle between 0 and the

upper extreme Dx (see pin 15).

If Dmax is the desired maximum duty cycle, the

voltage V3 to be applied to pin 3 is:

V3 =5 - 2

(2-Dmax)

(4)

Dmax is determined by internal comparison be-

tween V3 and the oscillator ramp (see fig. 22),

thus in case the device is synchronized to an ex-

ternal frequency fext (and therefore the oscillator

amplitude is reduced), (4) changes into:

= 5 − 4

⋅ exp 



−

Dmax

⋅ CT ⋅ fext







(5)

A voltage below 1V will inhibit the driver output

stage. This could be used for a not-latched device

disable, for example in case of overvoltage pro-

tection (see application ideas).

If no limitation on the maximum duty cycle is re-

quired (i.e. DMAX =DX), the pin has to be left float-

ing. An internal pull-up holds the voltage above

3V. Should the pin pick up noise (e.g. during ESD

tests), it can be connected to VREF through a

4.7k

Ω resistor.

Pin 4. VREF (Reference Voltage). An internal

generator furnishes an accurate voltage reference

(5V

±1.5%) that can be used to supply an external

circuit (consider some ten mA).

A small film capacitor (1

µF typ.), connected be-

tween this pin and SGND, is recommended to

preventswitching noise from affecting the reference.

Before device turn-on, this pin has a sink current ca-

pability of 0.5mA.

Pin 5. VFB (Error Amplifier Inverting Input). The

feedback signal is applied to this pin and is com-

pared to the E/A internal reference (2.5V). The

E/A output generates the control voltage which

fixes the duty cycle.

The E/A features high gain-bandwidth product,

which allows to broaden the bandwidth of the

overall control loop, high slew-rate and current

capability, which improves its large signal behav-

ior. Usually the compensation network, which sta-

bilizes the overall control loop, is connected be-

tween this pin and COMP (pin 6).

Pin 6. COMP (Error Amplifier Output). Usually,

this pin is used for frequency compensation and

the relevant network is connected between this

pin and VFB (pin 5). Compensation networks to-

wards ground are not possible since the L4990

E/A is a voltage mode amplifier (low output im-

pedance). See application ideas for some exam-

ple of compensation techniques.

Pin 7. SS (Soft-Start). At device start-up, a ca-

pacitor (Css) connected between this pin and

SGND (pin 12) is charged by an internal current

generator, ISSC, up to about 7V. During this

ramp, the E/A output is clamped by the voltage

across Css itself and allowed to rise linearly, start-

ing from zero, up to the steady-state value im-

posed by the control loop. The maximum time in-

terval during which the E/A is clamped, referred to

as soft-start time, is approximately:

D97IN501A

VREF

RCT

TO PWM LOGIC

Figure 22. Duty cycle control.

L4990 - L4990A

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