L4990AD datasheet(5/24 Pages) STMICROELECTRONICS

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referenced to 1.2V detects primary over-current

conditions. On detection of an overcurrent fault

the output is immediately shutdown and the fault

is also latched. A Fault Reset Delay is imple-

mented by discharging the external Soft Start

(SS) timing capacitor

before resetting the fault

latch and initiating a softstart cycle.

In case of a continuous fault condition the SS ca-

pacitor is charged to 5V before being discharged

again, to ensure that the fault frequency does not

exceed the programmed soft start frequency.

Duty Cycle Limit

A simple connection between the DC-LIM and the

available Vref activates an internal T- FlipFlop lim-

iting the DC to about 50%. If this pin is not con-

nected or grounded, the limit of the duty cycle is

extended to about 100%

Duty Cycle Control

Duty Cycle DC is externally programmed by set-

ting a voltage between 1V (0% DC) and 3V

(100% DC) at the DC pin. The programmed volt-

age is compared with the oscillator CT capacitor

charging waveform to determine the maximum

ON-time in each period. This function gives a fine

control of DC.

If this pin is floating the maximum duty cycle de-

pends on DC-LIM status.

Synchronization

A SYNC pin eases Synchronization of the IC to

the external world ( e.g.

another IC working in

parallel or to TV/monitor sync signal).

In TV/monitor applications the timing components

RT,CT are set for a frequency lower than the

minimum TV sync frequency. When the TV circuit

has powered-up it takes over and the system fre-

quency is that of the SYNC. Duty Cycle is control-

lable using the DC function.

In parallel operation of several IC’s no Mas-

ter/Slave designation is required as the higher fre-

quency IC is automatically the master. Controllers

to be synchronized have their SYNC pins tied to-

gether and each SYNC pin operates as a bidirec-

tional circuit. The first IC to drive its SYNC pin is

the master and it initiates a discharge of the CT

timing capacitor of every controller. The Sync in-

put signal is edge-triggered and sets an internal

”sync latch” which ensures full discharge of CT.

Disable Function

The DIS pin performs a logic level latched-shut-

down function. When pulled above 2.5V it shuts

down the complete IC with a standby current of

<270

µA (typ).

To reset the IC the VCC pin must be pulled-down

below the lower UVLO threshold (10V).

Leading Edge Blanking (LEB)

An LEB interval of 100ns has been incorporated

into the IC to blank out the current sense signal

during the first 100ns from switch turn-on.

This provides noise immunity to turn-on spikes

and reduces external RC filtering requirements on

the current-sense signal.

V1 4 = 0, O SC= disa bled

Tj = 25

°C

1 21 6

2 02 4

0.2

0.4

0.6

0.8

Vcc [V]

Iq [m A ]

Figure 1. Quiescent current vs. input voltage.

(X = 7.6V and Y = 8.4V for L4990A)

1012

141618

202224

21 0

24 0

27 0

30 0

Vcc

[V ]

[uA]

V14 = Vref

Tj = 25

°C

Figure 2. Quiescent current vs. input voltage

(after disable).

L4990 - L4990A

5/24

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