25CS160-HSLASHMS datasheet(2/53 Pages) MICROCHIP

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Preliminary

DS20007008B-page 2

25CS160

General Description

The Microchip Technology Inc. 25CS160 provides

16 Kbits of Serial EEPROM utilizing the Serial

Peripheral Interface (SPI) compatible bus. The device

is organized as 2,048 bytes of 8 bits each (2-Kbyte) and

is optimized for use in consumer and industrial

applications where reliable and dependable nonvolatile

memory storage is essential. The 25CS160 is capable

of operation across a broad voltage range (1.7V to

5.5V).

The bus signals required are a clock input (SCK) plus

separate data in (SI) and data out (SO) lines. Access to

the device is controlled through a Chip Select (CS)

input. Communication to the device can be paused via

the HOLD pin. While the device is paused, transitions

on its inputs will be ignored, with the exception of Chip

Select, allowing the host to service higher-priority

interrupts.

The 25CS160 features a nonvolatile Security register

independent of the 16-Kbit main memory array. The

first half of the Security register is read-only and

contains a factory-programmed, globally unique,

128-bit serial number in the first 16 bytes. The 128-bit

serial number is unique across the entire CS series of

Serial

EEPROM

products

and

eliminates

the

time-consuming step of performing and ensuring

serialization of a product on a manufacturing line.

The 128-bit read-only serial number is followed by an

additional 32 bytes of user-programmable EEPROM.

The user-programmable section of the Security

software sequence.

To protect against brown-out events, an undervoltage

lockout detection circuit inhibits all write sequences

when VCC supply voltage drops below the set voltage

level. The voltage level is configurable via the

Undervoltage Lockout Detection (UVLO) register.

For added reliability, the 25CS160 utilizes a built-in

Error Correction Code (ECC) scheme. This scheme

can correct up to one incorrectly read bit within a

one-byte readout. Additionally, the 25CS160 includes a

flag in the STATUS register to report if any errors were

detected and corrected in the most recent memory

array read sequence.

The 25CS160 features an Identification register that

contains identification information that can be read

from the device. This enables the application to

electronically query and identify the 25CS160 while it is

in the system. The identification method and the

instruction opcode comply with the JEDEC® standard

for “Manufacturer and Device ID Read Methodology for

SPI Compatible Serial Interface Memory Devices”.

The type of information that can be read from the

device includes the JEDEC®-defined Manufacturer ID,

the vendor-specific Device ID and the vendor-specific

Extended Device Information (EDI).

Bus Connections for the 25CS160

SPI MCU

Client 0

25XXX

SPI CK

MISO

MOSI

CS3 CS2 CS1 CS0

SO SCK

Client 1

25XXX

SO SCK

Client 2

25XXX

SO SCK

Client 3

25XXX

SO SCK

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