25CS160-HSLASHMS datasheet(21/53 Pages) MICROCHIP

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Preliminary

DS20007008B-page 21

25CS160

6.1.3

WRITE ENABLE LATCH

Enabling and disabling writing to any nonvolatile

is accomplished through the Write Enable (WREN)

instruction, as shown in Section 5.1 “Write Enable

Instruction (WREN)”, and the Write Disable (WRDI)

instruction, as shown in Section 5.2 “Write Disable

(WRDI) Instruction”. These functions change the

state of the Write Enable Latch (WEL) bit (byte 0, bit 1)

in the STATUS register.

A logic ‘1’ bit indicates that the device is currently busy

performing a nonvolatile write sequence. During this

time, only the Read STATUS Register (RDSR)

instruction will be executed by the device.

A logic ‘0’ bit in this position indicates the device is

ready to accept new instructions.

6.1.4

READY/BUSY STATUS LATCH

The Ready/Busy Status Latch (RDY/BSY) is used to

indicate whether the device is currently active in a

nonvolatile write sequence. This bit is read-only and

automatically updated by the device. It is provided in bit

0 of both STATUS register bytes.

A logic ‘1’ bit indicates that the device is currently busy

performing a nonvolatile write sequence. During this

time, only the Read STATUS Register (RDSR) and the

Write Ready/Busy Poll (WRBP) instructions will be

executed by the device.

A logic ‘0’ bit in this position indicates the device is

ready to accept new instructions.

6.1.5

ERROR CORRECTION STATE

LATCH

The Error Correction State (ECS) bit indicates whether

the on-chip Error Correction Code (ECC) logic scheme

was invoked during the previous read sequence. For

more information related to ECC, refer to Section 8.2

“Error Correction Code (ECC) Architecture”.

The ECS bit will be set to logic ‘0’ unless the previously

executed read sequence required the use of the ECC

logic scheme. When this occurs, the ECS bit will be set

to logic ‘1’.

The ECS bit will continue to read a logic ‘1’ until another

read sequence occurs where the use of the ECC logic

scheme is not required, a Power-On Reset (POR)

event occurs or a Software Device Reset (SRST)

instruction is sent to the 25CS160.

6.1.6

WRITE LOCKOUT STATE BIT

The Write Lockout State (WLS) bit is located in byte 1,

bit 2 of the STATUS register. This bit indicates whether

the last write sequence was inhibited by the UVLO

detection circuit (see Section 10.0 “Programmable

UnderVoltage Lockout”).

A logic ‘1’ in this bit position indicates that the previous

write sequence was inhibited by UVLO. A logic ‘0’

indicates the previous write sequence was not inhibited

by UVLO.

The WLS bit will continue to read out a logic ‘1’ until one

of the following occurs:

• A Power-On Reset (POR) event occurs

(Section 1.1.1 “Device Power-On Reset”)

• A nonvolatile write opcode is sent to the device

(WRITE, WRSR, WREX, LOCK, WUVL)

• A Software Device Reset (SRST) instruction is

executed

6.2

Read STATUS Register (RDSR)

The Read STATUS Register (RDSR) instruction

provides access to the contents of the STATUS

CS pin and then sending a 05h opcode. The device will

return the 16-bit STATUS register value on the SO pin.

The STATUS register can be continuously read for data

by continuing to read beyond the first 8-bit value

returned. The 25CS160 will update the value of the

RDY/BSY and WEL bits in the STATUS register upon

the completion of every eight bits, thereby allowing new

STATUS register values to be read without having to

issue a new RDSR instruction.

A new RDSR instruction needs to be initiated for the

nonvolatile bits (WPEN, BP0 and BP1) in the STATUS

Note:

The Write Lockout State (WLS) bit is only

valid if the undervoltage lockout function is

enabled.

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