AD8067

Rev. A | Page 16 of 24

INPUT PROTECTION

The inputs of the AD8067 are protected with back-to-back

diodes between the input terminals as well as ESD diodes to

either power supply. The result is an input stage with picoamp

level input currents that can withstand 2 kV ESD events

(human body model) with no degradation.

Excessive power dissipation through the protection devices

destroys or degrades the performance of the amplifier.

Differential voltages greater than 0.7 V result in an input

voltages beyond the positive supply, the input current is about

input current to 50 mA or less.

SUPPLY VOLTAGES

–

+

–

+

AD8067

FOR LARGE |V+ – V– |

Figure 46. Current Limiting Resistor

CAPACITIVE LOAD DRIVE

Capacitive load introduces a pole in the amplifier loop response

due to the finite output impedance of the amplifier. This can

cause excessive peaking and ringing in the response. The

AD8067 with a gain of +10 handles up to a 30 pF capacitive

load without an excessive amount of peaking (see Figure 8). If

greater capacitive load drive is required, consider inserting a

small resistor in series with the load (24.9 Ω is a good value to

start with). Capacitive load drive capability also increases as the

gain of the amplifier increases.

LAYOUT, GROUNDING, AND BYPASSING

CONSIDERATIONS

Layout

In extremely low input bias current amplifier applications, stray

leakage current paths must be kept to a minimum. Any voltage

differential between the amplifier inputs and nearby traces sets

up a leakage path through the PCB. Consider a 1 V signal and

100 GΩ to ground present at the input of the amplifier. The

resultant leakage current is 10 pA; this is 10× the input bias

current of the amplifier. Poor PCB layout, contamination, and

the board material can create large leakage currents. Common

contaminants on boards are skin oils, moisture, solder flux, and

cleaning agents. Therefore, it is imperative that the board be

thoroughly cleaned and the board surface be free of contaminants

to fully take advantage of the AD8067’s low input bias currents.

To significantly reduce leakage paths, a guard-ring/shield

around the inputs should be used. The guard-ring circles the

input pins and is driven to the same potential as the input

signal, thereby reducing the potential difference between pins.

For the guard ring to be completely effective, it must be driven

by a relatively low impedance source and should completely

surround the input leads on all sides, above, and below, using a

multilayer board (see Figure 47). The SOT-23-5 package

presents a challenge in keeping the leakage paths to a minimum.

The pin spacing is very tight, so extra care must be used when

constructing the guard ring (see Figure 48 for recommended

guard-ring construction).

NONINVERTING

GUARD RING

INVERTING

GUARD RING

Figure 47. Guard-Ring Configurations

+V

–IN

+IN

–V

AD8067

NONINVERTING

+V

–IN

+IN

–V

AD8067

INVERTING

Figure 48. Guard-Ring Layout SOT-23-5