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ADMV8809ACCZ-R7 数据表(PDF) 33 Page - Analog Devices

部件名 ADMV8809ACCZ-R7
功能描述  0.5GHz to 9GHz, Digitally Tunable, High-Pass Filters and Low-Pass Filters
PDF  55 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADMV8809ACCZ-R7 数据表(HTML) 33 Page - Analog Devices

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Data Sheet
ADMV8809
REGISTER DETAILS
analog.com
Rev. A | 33 of 55
Address: 0x0C, Reset: 0x00, Name: VARIANT
Figure 72.
Table 13. Bit Descriptions for VARIANT
Bits
Bit Name
Description
Reset
Access
[7:4]
RESERVED
Reserved.
0x0
R
[3:0]
VARIANT
Variant.
0x0
R
Address: 0x10, Reset: 0x00, Name: SPI_LEVEL_CTL
Figure 73.
Table 14. Bit Descriptions for SPI_LEVEL_CTL
Bits
Bit Name
Description
Reset
Access
[7:1]
RESERVED
Reserved.
0x0
R
0
SPI_LEVEL_CTL
Controls the SPI output level.
0x0
R/W
0: 1.8V.
1: 3.3V.
Address: 0x11, Reset: 0x0C, Name: LUT_CTL1
Figure 74.
Table 15. Bit Descriptions for LUT_CTL1
Bits
Bit Name
Description
Reset
Access
[7:4]
RESERVED
Reserved.
0x0
R
3
LUT_BYPASS
LUT Bypass.
0x1
R/W
0: Filters set by LUT.
1: Filters set by Register WR_SW and Register WR_FILTER.
2
LUT_LATCH
LUT Latch. Indicates if control output is latched (1) or combinational (0).
0x1
R/W
0: Control output is combinational.
1: Control output is latched.
1
LUT_MODE
LUT Mode.
0x0
R/W
0: LUT set by Register LUT_INDEX_POINTER.
1: LUT set by the parallel pins.
0
LUT_ACTIVE_SELECT
LUT Select.
0x0
R/W
0: LUT A.
1: LUT B.



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