ADMV8809ACCZ-R7 datasheet(22/55 Pages) AD

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Data Sheet

ADMV8809

THEORY OF OPERATION

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SPI CONFIGURATION

The SPI of the ADMV8809 allows configuration of the device for

specific functions or operations via the 5-pin SPI. This interface

provides users with added flexibility and customization. The SPI

consists of four control lines: SCLK, SDI, SDO, and CS .

The SPI protocol consists of an R/W bit followed by 15 register

address bits and 8 data bits. The address field and data field are

organized MSB first and end with the LSB.

Set the MSB to 0 for a write operation and set the MSB to 1 for a

read operation. The write cycle must be sampled on the rising edge

of SCLK. The 24 bits of the serial write address and data are shifted

in on the SDI control line, MSB to LSB. The ADMV8809 input logic

level for the write cycle supports a 3.3V interface.

For a read cycle, the R/W bit and the 15 register address bits shift

in on the rising edge of SCLK on the SDI control line. Then, 8 bits

of serial read data shift out on the SDO control line, MSB first, on

the falling edge of SCLK. The output logic level for a read cycle is

3.3V. The output drivers of the SDO are enabled after the last rising

edge of SCLK of the instruction cycle and remain active until the

end of the read cycle. In a read operation, when CS is deasserted,

SDO returns to high impedance until the next read transaction. CS

is active low and must be deasserted at the end of the write or read

sequence.

An active low input on CS starts and gates a communication cycle.

The CS pin allows more than one device to be used on the same

serial communications lines. The SDO pin goes to a high impe-

dance state when the CS input is high. During the communication

cycle, CS must stay low. The SPI communications protocol follows

the Analog Devices Inc, SPI standard. For more information, see

the ADI-SPI Serial Control Interface Standard (Rev 1.0).

CHIP ADDRESS

The four chip address pins enable the independent control of

multiple chips using the same SPI bus. In the 24-bit SPI frame, Bit

20 to Bit 17 are defined by the ADD3 to ADD0 pins.

A write instruction to Register 0x00 broadcasts to all chips in a

system regardless of the chip address pins.

Do not perform a read instruction of Register 0x00 in a multichip

system.

All references to register addresses in this section have the ADD3

to ADD0 pins set to zero, unless otherwise noted.

RF CONNECTIONS

The RF1 and RF2 pins of the ADMV8809 are DC-coupled to

on-chip ESD protection diodes. If a DC voltage is present on the

RF1 and RF2 pins from other components within the system, it is

recommended to place DC blocking capacitors in series with these

pins. The DC blocking capacitors must be selected based on the

operating frequency of the filter. Generally, a value greater than

10nF is sufficient to minimize insertion loss at the lower operating

frequencies. At higher operating frequencies, it may be necessary

to consider the parasitic elements of the selected capacitor. Fig-

ure 64 shows a general model of a capacitor with the parasitic

elements. The parasitic series inductance (LESL) is typically of

most concern given that its impedance can become dominant. The

other parasitic elements, including the leakage resistance (RL),

the dielectric absorption resistance (RDA), the dielectric absorption

capacitance (CDA), and electrical series resistance (RESR) are less

critical elements for consideration but are shown in Figure 64 for

completeness.

Figure 64. Model of a Capacitor

MODE SELECTION

The ADMV8809 has two modes of operation: SPI write and LUT

control. SPI write mode is the normal operating mode, whereas

the LUT control mode uses the 5-pin LUT control port to load the

configuration from the on-chip LUT.

To select SPI write mode, set the LUT_BYPASS bit (Bit 3) of

For operation in LUT control mode, set the LUT_BYPASS bit to 0.

SPI WRITE MODE

SPI write mode uses Register 0x13 (WR_SW) and Register 0x14

(WR_FILTER).

The WR_SW register includes the SW_SELECT bits can be used

to control which filter band the switches are toggled to.

The WR_FILTER register includes the FILTER_SELECT, HPF, and

LPF bits. Use the HPF and LPF bits (Bits[5:3] and Bits[2:0], respec-

tively) to configure the high-pass filter state and low-pass filter state

for each filter band. Use the FILTER_SELECT bits (Bits[7:6]) to

select the filter band that requires adjustment. The HPF and LPF bit

values dictate the new state for the HPF and LPF of the selected

filter band.

LUT CONTROL MODE

The ADMV8809 has a LUT feature that can be used to store

multiple filter conditions on LUT registers. See the Register Details

section for further information on the LUT registers.

There are two registers that control the functionality of the LUT

control mode for the ADMV8809. Register 0x11 (LUT_CTL1)

includes the LUT_BYPASS, LUT_LATCH, LUT_MODE, and

LUT_ACTIVE_SELECT bits (Bit 3, Bit 2, Bit 1, and Bit 0, respec-

tively). Use these bits to bypass the LUT, configure the output

(latched or combinational) and mode (using LUT_INDEX_POINTER

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