Format for write to the Dolphin DAC:

Write:

10 Bits

to DAC

dead

cycle

Bit

R/W-

S0

S1

ATT_ENB

(*)

A0 (1)

A1

D8

D9

1 cycle

min

D0

D1

D2

D3

D4

D5

D6

D7

1 cycle

min

(*) indicates a change in the specification.

If the ATT_ENB is a 1, then the DAC output attenuation will be enabled, and the attenuation will be what-

ever has been previously written in the VCM control register (this may include no attenuation at all). If the

bit is 0, the attenuator is disabled and high gain is forced.

Format for write to all other Dolphin registers:

Write:

10 Bits

to DAC

dead

cycle

Bit

R/W-

S0

S1

S2

A0 (1)

A1

D8

D9

1 cycle

min

D0

D1

D2

D3

D4

D5

D6

D7

1 cycle

min

Format for write to the chips other than the 12V combo:

Write:

1Byte

dead

cycle

Bit

R/W-

S0S1

S2A0A1A2A3

none (1)

D0

D1

D2

D3

D4

D5

D6

D7

none (1)

(1) There may not be a dead cycle between write addresses and their data bits when data is addressed to another chip on the serial port.

NOTE: All registers are accessible during POR to allow for in circuit testing. Appropriate functional chip changes may be occurring during the

reset.

Serial Port Timing Specifications

Parameter

From/To

Min.

Typ.

Max.

Units

45

ns

SCLK high to

invalid SDIO, read

0ns

valid SDIO to

SCLK high

10

ns

SCLK high to

invalid SDIO, write

5ns

CSELB low to

first falling clock

133

ns (1)

last rising clock to

133

ns (1)

CSELB high

(1) CSELB specifications apply to both read and write operations. Timing is only shown in the read operation digram.

Minimum Timing for non-dead bit operation:

Timing Parameter

Ref Point

Min.

Typ.

Max.

Units

SCLK Vdl to Vdh

56

ns

SCLK Vdh to Vdl

56

ns

Threshold voltage for SDIO, internal to Dolphin:

SDIO Logic

Threshold

1.0

1.2

1.7

V

L6256

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