Auxiliary Control Register

Address: 0111

Bit Function

Mnemonic

Init State

R/W

Bit #

Read 1 indicates:

Start (1)

START

xxx

W

0

N/A

VCM enable (2)

VC_EN

0

W

1

enabled (5)

Spindle enable (3)

SP_EN

0

W

2

enabled (5)

Thermal Limit

OVTEMP

0

R

3

Th Limit

Test Enable (7)

T_EN

0

W

4

enabled (5)

Software POR

SPOR

off

W

5

always 0 (5)

Spare

Register Brake

RBRAKE

disabled (4)

R/W

7

Braking * (6)

NOTES:

(1) Start disables slew rate control. It also changes the back EMF detection circuitry from 3 phase to single phase.

(2) shuts down active circuitry and drives to the ground state when 0. A transition on this bit is required to reactivate the VCM. see state dia-

gram.

(3) shuts down active circuitry and tristates when 0. A transition on this bit is required to reactivate the spindle circuitry. see state diagram.

(4) Writing to brake will cause a register park, then a brake sequence (an internal POR), without causing an external POR\. Thus, the rest of

the system including the processor will not be reset.

(5) Optional bits.

(6) The register brake function has been redesigned to allow use of a momentary, current limited brake during start mode only. Asserting this

bit overrides the CCTR or CPR register contents without disturbing them, and causes a brake on the spindle outputs.

Resetting the bit restores the previous state ( the outputs were in before the bit was asserted). DO NOT attempt to change the CCTR or

CPR, or send a SP_CLK while this bit is asserted.

(7) Test Enable is used to enable manufacturer specific test circuitry within the chip. This bit should be initialized with a 0 value and left at 0

at all times. Do not attempt to use this bit for any reason unless you have complete manufacturer specific information.

Test Register

Address: 1000

Bit Function

Init State

R/W

Read 1 indicates:

Bits: TBD

up to 16 read, 8 write

NOTE: The test register requires 2 level access. That is, the test enable bit in the Aux Control Register must be written to with a 1 or the test

register is locked out.

Status Register (read only)

Mnemonic

Address: 0100

Status Bit

High Indicates

Address

Dead Bit (unusable for timing reasons)

-

n/a

Bit 0

UV detect

UV_DET *

Undervoltage Occuring

Bit 1

Overtemperature Warning

TWARN

Exceeded Warning Temp

Bit 2

Overtemperature Shutdown

OVTEMP

Exceeded Shutdown Temp (1)

Bit 3

Version Number (2 bits)

VERS *

(2)

4 = Bit 0

5 =Bit 1

Vendor Number

VENDOR

(2)

Bit 6

Spindle Current Limit

SILIM

Current Has Exceeded

threshold (7) (8)

Bit 7

Dead Bit (unusable for timing reasons)

n/a

Bit 8

EMF XOR Output

EMFX

Changes state on XOR of

Comparator A, B, C

Bit 9

EMF A Comparator Output

EMFA

Positive High

Bit 10

DAC write

XOR

Write (3)

Bit 11

Transmission Error

TX_ERR *

CSELB occurs during active

transmission (4) (7)

Bit 12

Aux_Write

AUX_WR

Toggles (5)

Bit 13

Phase Detect

PH_DET

Correct PWM phasing (6)

Bit 14

Spindle Forward

SP_FWD *

Reports correct spindle

rotation direction

Bit 15

NOTE: the status register is readable during a POR\ for in circuit testability.

(1) Overtemperature Shutdown or Warning do not cause POR\. This arrangement allows graceful recovery from overtemperature conditions.

(2) Vendor bit = 0 for Unitrode, 1 for ST. Version number, Bits 0,1 allow 4 chip versions. For the Dolphin: Bit 0 = 1, Bit 1 = 0. This allows de-

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