AD8318ACPZ-R2 datasheet(12/24 Pages) AD

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AD8318

Rev. B | Page 12 of 24

USING THE AD8318

BASIC CONNECTIONS

The AD8318 is specified for operation up to 8 GHz. As a result,

low impedance supply pins with adequate isolation between

functions are essential. In the AD8318, VPSI and VPSO, the two

positive supply pins, must be connected to the same positive

potential. The VPSI pin biases the input circuitry, while the

VPSO pin biases the low noise output driver for VOUT.

Separate commons are also included in the device. CMOP is

used as the common for the output drivers. Pin CMIP and

Pin CMOP should be connected to a low impedance ground plane.

A power supply voltage of between 4.5 V and 5.5 V should be

applied to VPSO and VPSI. In addition, 100 pF and 0.1 μF

power supply decoupling capacitors connect close to each

power supply pin. The two adjacent VPSI pins can share a pair

of decoupling capacitors due to their proximity.

1SEE TEMPERATURE COMPENSATION SECTION.

2SEE RESPONSE TIME SECTION.

CMIP

TADJ

VPSO

CMIP

VPSI

TEMP

CMOP

INHI

VSET

INLO

VOUT

ENBL

CLPF

AD8318

100pF

0.1µF

1nF

499Ω

NOTE 1

100pF

0.1µF

52.3Ω

TEMP

INPUT

VOUT

NOTE 2

Figure 23. Basic Connections

The paddle of the AD8318 LFCSP is internally connected to

CMIP. For optimum thermal and electrical performance, solder

the paddle to a low impedance ground plane.

ENABLE INTERFACE

To enable the AD8318, the ENBL pin must be pulled high.

Taking ENBL low puts the AD8318 in sleep mode, reducing

current consumption to 260 μA at ambient. The voltage on

ENBL must be greater than 2 VBE (~1.7 V) to enable the device.

When enabled, the ENBL pin draws less than 1 μA. When

ENBL is pulled low, the pin sources 15 μA.

The enable interface has high input impedance. An internal

200 Ω resistor is placed in series with the ENBL input for added

protection. Figure 24 depicts a simplified schematic of the

enable interface. The response time of the AD8318 ENBL

interface is shown in Figure 25.

ENBL

CMIP

VPSI

2 × VBE

DISCHARGE

ENABLE

40kΩ

200Ω

40kΩ

Figure 24. ENBL Interface

CH1 500mV

M400ns

A CH1

920mV

Δ: 2.07V

@: 2.07V

425.200ns

Figure 25. ENBL Response Time; VPOS = 5.0 V;

Input AC-Coupling Caps = 18 pF; CLPF = Open

INPUT SIGNAL COUPLING

The RF input to the AD8318 (INHI) is single ended and must

be ac-coupled. INLO (input common) should be ac-coupled to

ground (see Figure 23). Suggested coupling capacitors are 1 nF

ceramic, 0402-style capacitors for input frequencies of 1 MHz to

8 GHz. The coupling capacitors should be mounted close to the

INHI pin and the INLO pin. These capacitor values can be

increased to lower the input stage high-pass cutoff frequency.

The high-pass corner is set by the input coupling capacitors and

the internal 10 pF capacitor. The dc voltage on INHI and INLO

is approximately one diode voltage drop below the voltage

applied to the VPSI pin.

The Smith Chart in Figure 16 shows the AD8318 input

impedance vs. frequency. Table 4 lists the reflection coefficient

and impedance at select frequencies. For Figure 16 and Table 4,

the 52.3 Ω input termination resistor is removed. At dc, the

resistance is typically 2 kΩ. At frequencies up to 1 GHz, the

impedance is approximated as 1000 Ω||0.7 pF. The RF input

pins are coupled to a network as shown in the simplified

schematic in Figure 26.

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