AD8139ACP-R2 datasheet(21/24 Pages) AD

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AD8139

Rev. B | Page 21 of 24

One way to avoid the input common-mode swing limitation is

to bias VIN and VREF at midsupply. In this case, VIN is 5 V p-p

swinging about a baseline at 2.5 V, and VREF is connected to a

low-Z 2.5 V source. VICM now has an amplitude of 2.5 V p-p and

is swinging about 2.5 V. Using the results in Equation 17, VACM

is calculated to be equal to VICM because VOCM = VICM. Therefore,

VACM swings from 1.25 V to 3.75 V, which is well within the

input common-mode voltage limits of the AD8139. Another

benefit seen in this example is that because VOCM = VACM = VICM

no wasted common-mode current flows. Figure 62 illustrates

how to provide the low-Z bias voltage. For situations that do not

require a precise reference, a simple voltage divider suffices to

develop the input voltage to the buffer.

VIN

0V TO 5V

AD8139

–

VOCM

200Ω

324Ω

200Ω

324Ω

0.1µF

10µF

AD8031

–

0.1µF

ADR431

2.5V

REFERENCE

TO AD7674 REFBUFIN

Figure 62. Low-Z 2.5 V Buffer

Another way to avoid the input common-mode swing limitation is

to use dual power supplies on the AD8139. In this case, the

biasing circuitry is not required.

Bandwidth vs. Closed-Loop Gain

The 3 dB bandwidth of the AD8139 decreases proportionally

to increasing closed-loop gain in the same way as a traditional

voltage feedback operational amplifier. For closed-loop gains

greater than 4, the bandwidth obtained for a specific gain can be

estimated as

)

MHz

300

(

−

OUT

(20)

or equivalently, β(300 MHz).

This estimate assumes a minimum 90° phase margin for the

amplifier loop, which is a condition approached for gains greater

than 4. Lower gains show more bandwidth than predicted by

the equation due to the peaking produced by the lower

phase margin.

Estimating DC Errors

Primary differential output offset errors in the AD8139 are due

to three major components: the input offset voltage, the offset

between the VAN and VAP input currents interacting with the

feedback network resistances, and the offset produced by the dc

voltage difference between the input and output common-mode

voltages in conjunction with matching errors in the feedback

network.

The first output error component is calculated as

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

Vo _

, or equivalently as VIO/β

(21)

where VIO is the input offset voltage. The input offset voltage of the

AD8139 is laser trimmed and guaranteed to be less than 500 μV.

The second error is calculated as

()

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

(22)

where IIO is defined as the offset between the two input bias

currents.

The third error voltage is calculated as

Vo_e3 = Δenr × (VICM − VOCM)

(23)

where Δenr is the fractional mismatch between the two

feedback resistors.

The total differential offset error is the sum of these three error

sources.

Other Impact of Mismatches in the Feedback Networks

The internal common-mode feedback network still forces the

output voltages to remain balanced, even when the RF/RG feedback

networks are mismatched. However, the mismatch will cause a

gain error proportional to the feedback network mismatch.

Ratio-matching errors in the external resistors degrade the

ability to reject common-mode signals at the VAN and VIN input

terminals, much the same as with a four-resistor difference

amplifier made from a conventional op amp. Ratio-matching

errors also produce a differential output component that is

equal to the VOCM input voltage times the difference between the

feedback factors (βs). In most applications using 1% resistors,

this component amounts to a differential dc offset at the output

that is small enough to be ignored.

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