L6260 datasheet(13/30 Pages) STMICROELECTRONICS

13 / 30 page

Frequency Locked Loop Coarse Counter (Reg 5)

This register contains the ”coarse” FLL counter

value for the FLL. This register gives a worst case

resolution of 16

µs with the worst case (i.e. slow-

est) 4MHz clock and has a valid range of 001 to

FFF hex.

Reg: 5

Name: FLL Coarse Counter Register

Type: Write Only

BIT

LABEL

DESCRIPTION

@POR

CLATCH BIT 0

FLL Coarse counter LSB

CLATCH BIT 1

CLATCH BIT 2

CLATCH BIT 3

CLATCH BIT 4

CLATCH BIT 5

CLATCH BIT 6

CLATCH BIT 7

CLATCH BIT 8

CLATCH BIT 9

CLATCH BIT 10

CLATCH BIT 11

FLL Coarse counter MSB

Frequency Locked Loop Fine Counter (Reg 6)

This register contains the ”fine” counter value of

the FLL. The worst case resolution (i.e. with a

4MHz clock) is 1

µs. It is important that the

most significant bit of this register must be a

zero when a write is made. Valid writes to this

Reg: 6

Name: FLL Fine Counter Register

Type: Write only.

BIT

LABEL

DESCRIPTION

@POR

FLATCH BIT 0

FLL Fine counter LSB

FLATCH BIT 1

FLATCH BIT 2

FLATCH BIT 3

FLATCH BIT 4

FLATCH BIT 5

FLATCH BIT 6

FLATCH BIT 7

FLATCH BIT 8

FLATCH BIT 9

FLATCH BIT 10

FLATCH BIT 11

FLL Fine counter MSB -NOTE: On a write to this register, this bit

must be zero.

L6260

13/30

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