L6260 datasheet(21/30 Pages) STMICROELECTRONICS

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both a mask counter (9 bits) and a delay counter

(11 bits). The period counter is automatically re-

set to count the next zero crossing period.

The clock used for the period and mask counters

is a function of the system clock. If the FCLK (the

system clock) is set to the 8-12MHz range then

the period and mask counters are clocked at 1/64

of the system clock, other wise the registers are

clocked at 1/32 of the system clock. The delay

counter clock is programmable via the SPIN COM

DLY bits in the Spin Control Register (2.8-2.11).

This value is used to divide down the system

clock. Since there is 60 electrical degrees be-

tween zero-crossings, the delay counter can pro-

vide 1.875 through to 28.125 electrical degree de-

lay at 1.875 degree increments.

When the period counter reaches zero, the mask-

ing of the zero-crossing starts (to avoid seeing

current recirculation spikes). The delay counter

then starts to count down and when it reaches

zero the masking of the BEMF is released so that

zero crossings can once again be detected. The

masking hides the commutation of the motor

which takes place during the mask.

The clocking frequency of the mask and delay

counters is identical. However, the delay is 11 bits

and the mask only 9 bits. This means that the

mask can provide 15 electrical degrees of mask-

ing time. In the System Control Register B, bit

MAKE_PHASE (4.11) a bit value of zero gives

this 15 electrical degrees mask time but a one

gives 7.5 electrical degrees of mask.

Speed Control & F.L.L.

The rotational position of the motor is inferred

from the BEMF wave form generated by the float-

ing coil. The chip uses the instant of a particular

zero-crossing and the period between successive

zero crossings to dictate the commutation tim-

ings. The complete control loop is on chip and the

speed is controlled by a reference clock FCLK.

The speed control loop uses a frequency locked

loop which in conjunction with an external compen-

sation network brings the frequency of the ta-

chometer signal to be equal to the internally gener-

ated reference frequency. The tachometer signal

can either be the BEMF signal divided down to a

once per mechanical revolution signal or an exter-

nally generated tachometer signal, sector burst.

The output of the speed control is a current de-

mand signal that goes to the Spindle Driver.

The spindle current and the commutation delay is

programmed via the Spin Control Register. There

is a ”fine” and a ”coarse” counter that defines the

speed of the motor.

In more detail, the two registers are used in con-

junction with two down counters which form a fre-

quency detector that in turn creates feedback

through to a charge pump to maintain the motors

speed regulation.

The course counter is 12 bits and is clocked at

1/64

th the rate of the frequency clock (FCLK). The

fine counter is clocked at 1/4th FCLK. The on chip

Frequency Locked Loop (FLL) uses the electrical

cycle pulses (”ec pulse”) to time the motors rota-

tion. Upon the first ec pulse, the course register’s

contents (loaded via the serial port) is loaded into

the internal course counter is then loaded from its

corresponding register. The fine counter then also

immediately starts to count down. In theory (but

not normally in run mode, possibly at start up) the

fine counter could count down through zero an

continue counting down the 2’s complement of

the original fine counter value.

The period between the start of the course counter

and the zero crossing during the fine counter op-

eration is the programmed period. Any differences

between the desired period and the ec pulse (zero

crossing) is the error in the transconductance loop

and corrective action is take by the charge pump.

This error is a number given from a counter starting

when the fine counter reaches zero and resetting

when the BEMF pulse occurs. The vice versa hap-

pens if the BEMF anticipate the ending of the fine

counter. The error number is loaded in REG. 7.

The course and fine counter arrangement is

guarateed to work in all possible circumstances (pro-

viding there is enough BEMF). For example if the

zero crossing is within or outside the fine window or

even if the zero crossing is in the course register

range. This system will even work if the zero crossing

occurs across multiple course/finecycles.

The FLL has a prescaler (defined by the System

Control Register bits EL_MECH and 8_12P (3.10

& 3.5) that changes the cycle counting mecha-

nism between electrical, 8 pole or 12 pole (i.e. di-

viding the ec clock by 1,4 or 6) respectively.

The procedure for setting the motor speed is as

follows:

let’s call T0 this quantity. T0 =

SPEED

Doing

⋅ 0.9 ⋅ FCLK

we obtain Ncourse e. g.

the number to load in the course register. If this

number exceed 4096 the desired speed is not

achievable. Let’s call ErrNc the decimal part of

Ncourse doing

⋅ 0.1 ⋅ Fclk

+ ErrNc ⋅ 16 we obtain Nfine e.g.

the number to load in the fine register. If this number

exceed 2048 all the procedure must be repeated

changing0.9 with 0.91 and 0.1 with 0.09 and so on.

The spindle is enabled via the System Control

Registers.

The slew rate is defined by attaching a resistor to

ground from the SPN_SLW pin. The current loop

has

compensation RC

network

the

SPN_I_COMP pin and the sense resistor is at-

tached to the SPN_I_SNS pin (to ground).

L6260

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