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ADMV1455BBCZ-R7 数据表(PDF) 18 Page - Analog Devices |
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ADMV1455BBCZ-R7 数据表(HTML) 18 Page - Analog Devices |
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18 / 141 page  Data Sheet ADMV1455 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS analog.com Rev. 0 | 18 of 141 Table 17. Pin Function Descriptions (Continued) Pin No. Mnemonic Description K12 CS SPI Chip Select. Active low, 1.8V logic. Bring CS low to begin a SPI transaction, see Figure 167 and Figure 168 for more information. L2 ADD_G0 Gain LUT Address Bit 0. Active high, 1.8V logic. No internal pull-up or pull-down resistance. Tie ADD_G0 to the logic output from a microcontroller or FPGA; do not float. If ADD_G0 is not used to set the LUT address pointer, ground this ball. L10 VDD_LO LO Supply Voltage, 1.8V. Place 0.01μF and 1μF decoupling capacitors close to VDD_LO. L11 VDD_BG Band-Gap Reference Supply Voltage, 1.8V. Place 0.01μF and 1μF decoupling capacitors close to VDD_BG. Ideally for proper NVM load operation, apply the VDD_BG voltage after all other supplies have been turned on and RST has been set high. If this is not possible, as is the case if all supply voltages are applied together, ensure to set RST high and run the NVM refresh commands. |
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