DA9213 datasheet(36/62 Pages) RENESAS

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DA9213, DA9214, DA9215 Datasheet

R16DS0598EJ0361 Rev.03.61

Nov 03, 2025

CFR0011-120-00

Page 36

Parameters

Transmission

Half-duplex

MSB first

16-bit cycles

7-bit address, 1-bit read/write, 8-bit data

Configuration

CPOL

Clock polarity

CPHA

Clock phase

nCS_POL

nCS is active low/high

Note 1

Reading the same register at high clock rates directly after writing it does not guarantee a correct value. It is

recommended to keep a delay of one frame until re-accessing a register that has just been written (for example, by

writing/reading another register address in-between).

5.4.2

2-WIRE Communication

The IF_TYPE bit in the INTERFACE2 register can be used to configure the DA9213, DA9214, and DA9215

control interface as a 2-WIRE serial data interface. In this case the GPIO3 and GPI4 are free for regular

input/output functions. DA9213, DA9214, and DA9215 has a configurable device write address (default: 0xD0)

and a configurable device read address (default: 0xD1). See control IF_BASE_ADDR1 for details of configurable

addresses. The ADDR_SEL_CONF bit is used to configure the device address as IF_BASE_ADDR1 or

IF_BASE_ADDR2 depending on the voltage level applied at a configurable GPI port (see section 5.2.4).

The SK port functions as the 2-WIRE clock and the SI port carries all the power manager bidirectional 2-WIRE

data. The 2-WIRE interface is open-drain supporting multiple devices on a single line. The bus lines have to be

pulled HIGH by external pull-up res

istors (in the 2 kΩ to 20 kΩ range). The attached devices only drive the bus

lines LOW by connecting them to ground. As a result, two devices cannot conflict if they drive the bus

simultaneously. In standard/fast mode the highest frequency of the bus is 400 kHz. The exact frequency can be

determined by the application and does not have any relation to the DA9213, DA9214, and DA9215 internal

clock signals. DA9213, DA9214, and DA9215 will follow the host clock speed within the described limitations,

and does not initiate any clock arbitration or slow down. An automatic interface reset can be triggered using

control 2WIRE_TO if the clock signal stops to toggle for more than 35 ms.

The interface supports operation compatible to Standard, Fast, Fast-Plus and High-Speed mode of the I2C-bus

specification Rev 4. Operation in high-speed mode at 3.4 MHz requires mode changing in order to set spike

suppression and slope control characteristics to be compatible with the I2C-bus specification. The high-speed

mode can be enabled on a transfer-by-transfer basis by sending the master code (0000 1XXX) at the beginning

of the transfer. DA9213, DA9214, and DA9215 do not make use of clock stretching, and deliver read data

without additional delay up to 3.4 MHz.

Alternatively, PM_IF_HSM configures the interface to use high speed mode continuously. In this case, the

master code is not required at the beginning of every transfer. This reduces the communication overhead on the

bus but limits the slaves attachable to the bus to compatible devices.

The communication on the 2-WIRE bus always takes place between two devices, one acting as the master and

the other as the slave. The DA9213, DA9214, and DA9215 will only operate as a SLAVE.

In contrast to the 4-WIRE mode, the 2-WIRE interface has direct access to two pages of the register map (up to

256 addresses). The register at address zero on each page is used as a page control register (with the 2-WIRE

bus ignoring the LSB of control REG_PAGE). Writing to the page control register changes the active page for all

subsequent read/write operations unless an automatic return to page 0 was selected by asserting control

REVERT. Unless REVERT was asserted after modifying the active page, it is recommended to read back the

page control register to ensure that future data exchange is accessing the intended registers.

In 2-WIRE operation DA9213, DA9214, and DA9215 offer an alternative way to access register page 2 and page

3. It removes the need for preceding page selection writes by incrementing the device write/read address by one

(default 0xD2/0xD3) for any direct access of page 2 and page 3 (page 0 and 1 access requires the basic

write/read device address with the MSB of REG_PAGE to be 0).

5.4.3

Details of the 2-WIRE Control Bus Protocol

All data is transmitted across the 2-WIRE bus in groups of eight bits. To send a bit the SDA line is driven towards

the intended state while the SCL is LOW (a low on SDA indicates a zero bit). Once the SDA has settled, the SCL

line is brought HIGH and then LOW. This p

ulse on SCL clocks the SDA bit into the receiver’s shift register.

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