Data Sheet

ADPA7005

APPLICATIONS INFORMATION

analog.com

Rev. A | 17 of 24

Figure 52 shows the basic connections for operating the

ADPA7005. All measurements for this device were taken using the

typical application circuit shown in Figure 52.

Capacitive bypassing is required for all VGGx and VDDx pins.

VGG1 and VGG2 are the gate bias pins, and VDD1 to VDD6 are

the drain bias pins to the cascaded amplifier.

The power supply and gate voltage decoupling capacitors shown in

Figure 52 represent the configuration that was used to characterize

and qualify the device. It may be possible to reduce the number

of capacitors; however, this modification can vary from system to

system. It is recommended to first remove or combine the largest

capacitors that are farthest from the device. The following is the

recommended bias sequence during power-up:

1. Connect the power supply ground to circuit ground (GND).

2. Set the VGGx gate bias voltages to −1.5 V.

3. Set all VDDx drain bias voltages to 5 V.

4. Increase the VGGx gate bias voltages to achieve the quiescent

supply current and set IDQ = 1400 mA.

5. Apply the RF signal.

The following is the recommended bias sequence during power-

down:

1. Turn off the RF signal.

2. Decrease the VGGx gate bias voltages to −1.5 V to achieve an

IDQ = 0 mA (approximately).

3. Decrease all VDDx drain bias voltages to 0 V.

4. Increase the VGGx gate bias voltages to 0 V.

The VDD = 5 V and IDQ = 1400 mA bias conditions are recommend-

ed to optimize overall performance when the gate voltage is being

held at a fixed value (note that with the gate voltage held at a

fixed value, the drain current, IDD, increases as the RF input power

level is increased, as shown in Figure 41). Unless otherwise noted,

the data shown was taken using the recommended bias conditions.

Operation of the ADPA7005 at different bias conditions can result

in different performance. Biasing the ADPA7005 for higher IDQ

typically results in higher gain and output P1dB at the expense of

increased power dissipation (see Table 9).

Table 9. Power Selection1, 2

IDQ (mA)

Gain (dB)

Output P1dB (dBm)

Output IP3 (dBm)

PDISS (W)

VGGx (V)

1200

15.80

31.89

42.90

6

–0.73

1400

16.20

31.93

41.30

7

–0.68

1600

16.50

31.95

39.55

8

–0.63

1 Data taken at the following nominal bias conditions: VDD = 5 V, TCASE = 25°C, frequency = 32 GHz.

2 Adjust VGG1 and VGG2 from −1.5 V to 0 V to achieve the desired IDQ.