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MPC7447 数据表(PDF) 36 Page - Freescale Semiconductor, Inc |
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MPC7447 数据表(HTML) 36 Page - Freescale Semiconductor, Inc |
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36 / 60 page  MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4 36 Freescale Semiconductor System Design Information 100110 11x 1x 733 825 913 1100 1467 000000 11.5x 1x 766 863 955 1150 1533 101110 12x 1x 600 800 900 996 1200 1600 111110 12.5x 1x 625 833 938 1038 1250 1667 010110 13x 1x 650 865 975 1079 1300 111000 13.5x 1x 675 900 1013 1121 1350 110010 14x 1x 700 933 1050 1162 1400 000110 15x 1x 750 1000 1125 1245 1500 110110 16x 1x 800 1066 1200 1328 1600 000010 17x 1x 850 1132 1275 1417 1700 001010 18x 1x 600 900 1200 1350 1500 001110 20x 1x 667 1000 1332 1500 1666 010010 21x 1x 700 1050 1399 1575 011010 24x 1x 800 1200 1600 111010 28x 1x 933 1400 001100 PLL bypass PLL off, SYSCLK clocks core circuitry directly 111100 PLL off PLL off, no core clocking occurs Notes: 1. PLL_CFG[0:5] settings not listed are reserved. 2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the MPC7448; see Section 5.2.1, “Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies. 3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be driven at half the frequency of SYSCLK and offset in phase to meet the required input setup tIVKH and hold time tIXKH (see Table 9). The result will be that the processor bus frequency will be one-half SYSCLK, while the internal processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 4. In PLL-off mode, no clocking occurs inside the MPC7448 regardless of the SYSCLK input. 5. Applicable when DFS modes are disabled. These multipliers change when operating in a DFS mode. See Section 9.7.5, “Dynamic Frequency Switching (DFS)” for more information. 6. Bus-to-core multipliers less than 5x require that assertion of AACK be delayed by one or two bus cycles to allow the processor to generate a response to a snooped transaction. See the MPC7450 RISC Microprocessor Reference Manual for more information. Table 12. MPC7448 Microprocessor PLL Configuration Example (continued) PLL_CFG[0:5] Example Core and VCO Frequency in MHz Bus-to-Core Multiplier 5 Core-to-VCO Multiplier 5 Bus (SYSCLK) Frequency 33.3 MHz 50 MHz 66.6 MHz 75 MHz 83 MHz 100 MHz 133 MHz 167 MHz 200 MHz |
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