L9230

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SPI INTERFACE

The timing of L9230 is defined as follows:

- The change at output (SO) is forced by the rising edge of the SCK signal.

- The input signal (SI) is taken over on the falling edge of the SCK signal.

- SS = active without any clocks at SCK is not allowed

- The data received during a writing access is taken over into the internal registers on the rising edge of the SS

signal, if exactly 16 SPI clocks have been counted during SS = active.

Figure 6.

ELECTRICAL CHARACTERISTCS ( continued)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Input SCK (SPI clock input 4.5V < DMS < 5.5V)

Low Level

1

V

High Level

2

V

0.1

0.4

V

Input Capacity

10

pF

SO

SI

MSB IN

Bit (n-4)...1 LSB IN

Bit (n-4)...1

1

4

5

6

SCK

SS

7

8

n = 16

9

10

3

2

Bit (n-3)

Bit 0; LSB

tristate

Bit (n-3)

Bit (n-2)

11

12

ELECTRICAL CHARACTERISTICS (continued)