L9805 datasheet(32/103 Pages) STMICROELECTRONICS

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L9805

5.2 16-BIT TIMER

5.2.1 Introduction

The timer consists of a 16-bit free-running counter

driven by a programmable prescaler.

It may be used for a variety of purposes, including

pulse length measurement of up to two input sig-

nals (input capture) or generation of up to two out-

put waveforms (output compare and PWM).

Pulse lengths and waveform periods can be mod-

ulated from a few microseconds to several milli-

seconds using the timer prescaler and the CPU

clock prescaler.

5.2.2 Main Features

Programmable prescaler: fcpu divided by 2, 4 or 8.

Overflow status flag and maskable interrupt

External clock input (must be at least 4 times

slower than the CPU clock speed) with the choice

of active edge

Output compare functions with

– 2 dedicated 16-bit registers

– 2 dedicated programmable signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

Input capture functions with

– 2 dedicated 16-bit registers

– 2 dedicated active edge selection signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

Pulse width modulation mode (PWM)

One pulse mode

5 alternate functions on I/O ports

The Block Diagram is shown in Figure 16, on

page 33.

Note: Some external pins are not available on all

devices. Refer to the device pin out description.

5.2.3 Functional Description

5.2.3.1 Counter

The principal block of the Programmable Timer is

a 16-bit free running counter and its associated

16-bit registers:

Counter Registers

– Counter High Register (CHR) is the most sig-

nificant byte (MSB).

– Counter Low Register (CLR) is the least sig-

nificant byte (LSB).

Alternate Counter Registers

– Alternate Counter High Register (ACHR) is the

most significant byte (MSB).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LSB).

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (overflow

flag), (see note page 3).

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in Table 7 Clock

Control Bits. The value in the counter register re-

peats every 131.072, 262.144 or 524.288 internal

processor clock cycles depending on the CC1 and

CC0 bits.

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