L9805 datasheet(49/103 Pages) STMICROELECTRONICS

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L9805

5.3 PWM GENERATOR

5.3.1 Introduction

This PWM peripheral includes a 16-bit Pulse

Width Modulator (PWM) and a programmable

prescaler able to generate an internal clock with

period as long as 128*T

CPU.

The repetition rate of the 16-Bit PWM output can

be defined by a dedicated register (fCPU/CYREG);

its resolution is defined by the internal clock as per

the prescaler programming.

Main Features

-Programmable prescaler: fCPU divided by 2, 4, 8,

16, 32, 64 or 128.

-1 control register

-2 dedicated 16-bit registers for cycle and duty

control

-1 dedicated maskable interrupt

Procedure

To use the pulse width modulation peripheral, the

EN_PWM bit in CONREG register must be set.

Load PS(2:0) in CONREG register to define the

programmable prescaler.

Load the CYREG register with the value defining

the cycle length (in internal clock periods). The 16

bits of this register are separated in two registers:

CYREGH and CYREGL.

Load the DUTYREG register with the value corre-

sponding to the pulse length (in internal cycle peri-

ods). The 16 bits of this register are separated in

two registers: DUTYREGH and DUTYREGL.

The counter is reset to zero when EN_PWM bit is

reset.

Writing the DUTYREG and CYREG registers has

no effect on the current PWM cycle. The cycle or

duty cycle change take place only after the first

overflow of the counter.

The suggested procedures to change the PWM

parameters are the following:

Duty Cycle control:

- Write the low and high DUTYREG registers.

A writing only on one DUTYREG register has no

effect until both registers are written.

The current PWM cycle will be completed. The

new duty cycle will be effective at the following

PWM cycle, with respect to the last DUTYREG

writing.

Cycle control:

- Write the low and high CYREG register

A writing only on one CYREG register has no ef-

fect until both registers are written.

The current PWM cycle will be completed. The

new cycle will be effective at the following PWM

cycle, with respect to the last CYREG writing.

Another possible procedure is:

- Reset the EN_PWM bit.

- Write the wanted configuration in CYREG and

DUTYREG..

- Set the EN_PWM bit.

If the EN_PWM bit is set after being reset, the cur-

rent values of DUTYREG and CYREG are deter-

mining the output waveform, no matter if only the

low or the high part, or both were written.

The first time EN_PWM is set, if CYREG and DU-

TYREG were not previously written, the output is

permanently low, because the default value of the

registers is 00h.

Changing the Prescaler ratio writing PS(2:0) in

CONREG has immediate effect on the waveform

frequency.

5.3.2 Functional Description

The PWM module consists of a 16-bit counter, a

comparator and the cycle generation logic.

PWM Generation

The counter increments continuously, clocked at

internal clock generated by prescaler. Whenever

the 16 bits of the counter (defined as the PWM

counter) overflow, the output level is set. The over-

flow value is defined by CYREG register.

The state of the PWM counter is continuously

compared to the PWM binary weight, as defined in

DUTYREG register, and when a match occurs the

output level is reset.

Figure 26. PWM Cycle

Note: If the CYREG value is minor or equal than

DUTYREG value, PWM output remains set. With a

Counter

Counter is reset

OUT PWM = 1

Counter

= CYREG

OUT PWM = 0

When

= DUTYREG

Pulse Width Modulation cycle

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