L9805 datasheet(45/103 Pages) STMICROELECTRONICS

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L9805

16-BIT TIMER (Cont’d)

STATUS REGISTER (SR)

Timer1 Register Address: 0033h

Timer2 Register Address: 0043h

Read Only

Reset Value: 0000 0000 (00h)

The three least significant bits are not used.

Bit 7 = ICF1 Input Capture Flag 1.

0: No input capture (reset value)

1: An input capture has occurred. To clear this bit,

first read the SR register, then read or write the

low byte of the ICR1 (ICLR1) register.

Bit 6 = OCF1 Output Compare Flag 1.

0: No match (reset value)

1: The content of the free running counter has

matched the content of the OCR1 register. To

clear this bit, first read the SR register, then read

or write the low byte of the OCR1 (OCLR1) reg-

ister.

Bit 5 = TOF Timer Overflow.

0: No timer overflow (reset value)

1: The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR reg-

ister, then read or write the low byte of the CR

(CLR) register.

Note: Reading or writing the ACLR register do not

clear TOF.

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value)

1: An input capture has occurred.To clear this bit,

first read the SR register, then read or write the

low byte of the ICR2 (ICLR2) register.

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value)

1: The content of the free running counter has

matched the content of the OCR2 register. To

clear this bit, first read the SR register, then read

or write the low byte of the OCR2 (OCLR2) reg-

ister.

Bit 2-0 = Unused.

ICF1

OCF1

TOF

ICF2

OCF2

L9805 数据表(PDF) 45 Page - STMicroelectronics

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