13/20

L9949

rising edge of the CLK signal and shifted into an internal 16 bit shift register. At the rising edge of the CSN signal

the contents of the shift register will be transfered to Data Input Register (see FIGURE 8).

The SPI uses an internal 16 bit counter which will be reset at the rising edge of the CSN signal. Only the first 16

bits of the data input DI will be relevant. If more than 16 bits are transfered the trailing bits will be ignored.

Serial Data Out (DO)

The output driver is activated by a logical low level at the CSN input and will go from high impedance to a low

or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to

low transition of the CSN pin will transfer the content of the selected status register into the data out shift register.

Each subsequent falling edge of the CLK will shift the next bit out.

Serial Clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at

the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal (see

FIGURE 8).

Input Data Register

After the rising edge of CSN the contents of the input shift register will be written to the input data register. De-

pending on bit 0 the contents of the selected status register will be transfered to DO during the current commu-

nication cycle. Bit 1-11 controls the behaviour of the corresponding driver. If bit 12 and bit 13 are zero, the device

will go into the standby-mode. If at least one of both bits are one these bits will be used to control the current

is used to reset all status bits in both status registers. The bits in the status registers will be cleared after the

current communication cycle (rising edge of CSN).

Status Register

This devices uses two status registers to store and to monitor the state of the device. Bit 0 is used as a fault bit

and is a logical-NOR combination of all other bits in both status registers. The state of this bit can be polled by

the microcontroller without the need of a full SPI-communication cycle (see FIGURE 13). If one of the overcur-

rent bits is set, the corresponding driver will be disabled. The microcontroller has to clear the overcurrent bit to

enable the driver. If the thermal shutdown bit is set, all drivers will go into a high impedance state. Again the

microcontroller has to clear the bit to enable the drivers. The behaviour of the device in case of an over- or un-

action from the microcontroller is needed.

Test Mode

Due to the current limitations of a single bond wire the output stages OUT1, 2 and 6 need two bond wires in

parallel. For the full output current driving capability it is necessary to check that both bond wires are connected

correctly to the lead frame. Therefore the drivers and DMOS-transistors of the outputs OUT1, 2 and 6 are split-

ted into two independet stages, one for each bond wire (see FIGURE 6.4). In normal operating mode the splitted

outputs are connected in parallel. In the test mode bit 5 and 6 of the input data register select the A-driver, bit 7

and 8 the B-driver. If all four bits (5 - 8) are switched to high level, no driver will be activated. For all combinations

beside both high of bit 5 and 6 or bit 7 and 8 the output stages OUT3 and OUT4 are controlled like in normal

operating mode. In any case the output stages are protected against shoot through current. Furthermore the

inputs CLK and DI are connected by an OR to the output DO for testing the threshold voltages and the hyster-

esis. The input CLK can be tested by clamping the input DI to low level and vice versa.