L9949

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Figure 8. SPI-Interface - Transfer Timing Diagram

Tristate Leakage Current

-10

10

Tristate Input Capacitance

10

15

pF

DO timing (see Figg. 10 & 11)

DO Rise Time

50

100

ns

Data Out Fall Time

50

100

ns

from tristate to low level

80

250

ns

from low level totristate

200

400

ns

from tristate to high level

pull-down load to GND

80

250

ns

from high level totristate

ppull-down load to GND

200

400

ns

DO Delay Time

50

250

ns

(1)

Value of input capacity is not measured in production test. Parameter guarenteed by design.

(2)

DI timing parameters tested in production by a passed/failed test:

Tj=-40°C/+25°C: SPI communication @2MHz

Tj=+125°C:

SPI communication @1.25MHz

SPI INTERFACE ELECTRICAL CHARACTERISTCS (continued)

GND and currents are assumed positive, when the current flows into the pin

.

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

0

1

0

1

time

time

time

time

time

CSN high to low: DO enabled

actual data

DI: data will be accepted on the rising edge of CLK signal

new data

CSN

CLK

DI

DO

e.g.OUT1

DO: data will change on the falling edge of CLK signal

status information

fault bit

CSN low to high: actual data is

transfered to output power switches

old data

12

3

4

5

6

78

9

10 11

012

13 14 15

1

0

actual

l

data

1

2

3

456

78

9

10 11

012

13 14 15

1

2

3

456

78

9

10 11

012

13 14 15