15/20

L9949

SPI INTERFACE ELECTRICAL CHARACTERISTCS

GND and currents are assumed positive, when the current flows into the pin

.

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Delay time from standby to active mode

Delay Time

Switching from standby to active

mode. Time until output drivers are

enabled after CSN going to high.

200

Inputs: CSN, CLK and DI

Input Low Level

1.5

V

Input High Level

3.5

V

Input Hystersis

0.5

V

Pull Up Current at input CSN

-50

-25

-10

µA

Pull Down Current at input CLK

10

25

50

µA

Pull Down Current at input DI

10

25

50

µA

(1)

Input Capacitance at input CSN

or CLK

10

15

pF

Clock Period

1000

ns

Clock High Time

400

ns

Clock Low Time

400

ns

CSN setup time, CSN low before

rising edge of CLK

400

ns

CLK setup time, CLK high before

rising edge of CSN

400

ns

DI setup time

200

ns

DI hold time

200

ns

Rise Time of Input Signal

DI, CLK, CSN

100

ns

Fall Time of Input Signal

DI, CLK, CSN

100

ns

DO

Output Low Level

0.2

0.4

V

Output High Level

-1.3

-1.0

V

-0.8

V