STM32L4P5CEU6P datasheet(203/311 Pages) STMICROELECTRONICS

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DS12903 Rev 2

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STM32L4P5xx

Electrical characteristics

277

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 36 for standard I/Os, and in Figure 36 for

5 V tolerant I/Os.

Figure 36. I/O input characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or

source up to ± 20 mA (with a relaxed VOL/VOH).

In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 6.2:

•

The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum

consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating

ΣIVDD (see Table 18: Voltage characteristics).

•

The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of

the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see

Table 18: Voltage characteristics).

6. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:

ITotal_Ileak_max = 10 μA + [number of IOs where VIN is applied on the pad] x Ilkg(Max).

7. To sustain a voltage higher than MIN(VDD, VDDA, VDDUSB, VDDIO2) +0.3 V, the internal Pull-up and Pull-Down resistors must

be disabled.

8. Refer to Ibias in Table 87: OPAMP characteristics for the values of the OPAMP dedicated input leakage current.

9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

MSv37613V2

Teste

d in

production

CMOS

requirement

Vih

min

= 0

.7xV

DDIO

Based

on simula

tion Vi

h min

= 0.6

1xVDDIOx

+0.05

for 1.08<V

DDIOx

<1.62

or 0.49xV

DDIOx

+0.2

6 for

VDDI

Ox>1

.62

Based

on simu

lation

Vil m

ax =0.43xV

DDIOx

-0.1 for

1.08

<VDDIOx

<1.62

or 0.39xV

DDIOx

-0.06

for VDDIO

x>1.62

Tested

in produ

ction CMOS

requirement

Vil ma

x = 0.3xVdd

TTL requirement Vih min = 2V

TTL requirement Vil max = 0.8V

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