M14256, M14128

8/12

tive addresses, with the internal address counter

automatically incremented after each byte output.

After the last memory address, the address

counter will ‘roll-over’ and the memory will contin-

ue to output data from the start of the memory

block.

Acknowledge in Read Mode

In all read modes the memory waits for an ac-

does not pull the SDA line low during this time, the

memory terminates the data transfer and switches

to its standby state.

the RW bit set to ‘1’. The memory acknowledges

this, and outputs the byte addressed. The master

must

nates the transfer with a STOP condition.

Sequential Read

This mode can be initiated with either a Current

Address Read or a Random Address Read. How-

ever, in this case the master

the data byte output, and the memory continues to

output the next byte in sequence. To terminate the

stream of bytes, the master must

the last byte output, and

condition. The output data comes from consecu-

Figure 8. Read Mode Sequences

DEV SEL *

BYTE ADDR

BYTE ADDR

DEV SEL

DATA OUT 1

AI01105C

DATA OUT N

CURRENT

ADDRESS

READ

DEV SEL

DATA OUT

RANDOM

ADDRESS

READ

DEV SEL *

DATA OUT

SEQUENTIAL

CURRENT

READ

DATA OUT N

DEV SEL *

BYTE ADDR

BYTE ADDR

SEQUENTIAL

RANDOM

READ

DEV SEL *

DATA OUT 1

ACK

R/W

NO ACK

ACK

R/W

ACK

ACK

ACK

R/W

ACK

ACK

ACK

NO ACK

R/W

NO ACK

ACK

ACK

ACK

R/W

ACK

ACK

R/W

ACK

NO ACK