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M14C16, M14C04

Random Address Read

A dummy write is performed to load the address

into the address counter, as shown in Figure 8.

This is followed by another START condition from

the master and the device select is repeated with

the RW bit set to ‘1’. The memory acknowledges

this, and outputs the byte addressed. The master

must

nates the transfer with a STOP condition.

Sequential Read

This mode can be initiated with either a Current

Address Read or a Random Address Read. How-

ever, in this case the master

the data byte output, and the memory continues to

output the next byte in sequence. To terminate the

stream of bytes, the master must

the last byte output, and

condition. The output data comes from consecu-

tive addresses, with the internal address counter

automatically incremented after each byte output.

with an ACK, indicating that the memory is

ready to receive the second part of the next in-

struction (the first byte of this instruction having

been sent during Step 1).

Read Operations

Read operations are independent of the state of

the WC pin. On delivery, the memory content is set

at all “1’s” (FFh).

Current Address Read

The memory has an internal address counter.

Each time a byte is read, this counter is increment-

ed. For the Current Address Read mode, following

a START condition, the master sends a device se-

lect with the RW bit set to ‘1’. The memory ac-

knowledges this, and outputs the byte addressed

by the internal address counter. The counter is

then incremented. The master must

edge the byte output, and terminates the transfer

with a STOP condition, as shown in Figure 8.

Figure 7. Write Cycle Polling Flowchart using ACK

WRITE Cycle

in Progress

AI02165

Next

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

NO

YES

NO

ReSTART

STOP

Proceed

WRITE Operation

Proceed

Random Address

READ Operation

Send

Byte Address

First byte of instruction

with RW = 0 already

decoded by M14xxx