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M14C16, M14C04

Figure 5. Write Mode Sequences with WC=1

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

WC

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

WC

DATA IN 3

AI02803B

PAGE WRITE

(cont'd)

WC (cont'd)

DATA IN N

ACK

ACK

NO ACK

R/W

ACK

ACK

NO ACK

NO ACK

R/W

NO ACK

NO ACK

Byte Write

In the Byte Write mode, after the Device Select

code and the address, the master sends one data

byte. If the addressed location is write protected by

the WC pin, the memory replies with a NoACK,

and the location is not modified. If, instead, the WC

pin has been held at 0, as shown in Figure 6, the

memory replies with an ACK. The master termi-

nates the transfer by generating a STOP condi-

tion.

Page Write

The Page Write mode allows up to 16 bytes to be

written in a single write cycle, provided that they

are all located in the same ’row’ in the memory:

that is the most significant memory address bits

(b10-b4 for the M14C16 and b8-b4 for the

M14C04) are the same. The master sends from

one up to 16 bytes of data, each of which is ac-

knowledged by the memory if the WC pin is low. If

the WC pin is high, each data byte is followed by a

NoACK and the location is not modified. After each

byte is transferred, the internal byte address coun-

ter (the four least significant bits only) is incre-

mented. The transfer is terminated by the master

generating a STOP condition. Care must be taken

to avoid address counter ’roll-over’ which could re-

sult in data being overwritten. Note that, for any

byte or page write mode, the generation by the

master of the STOP condition starts the internal

memory program cycle. This STOP condition trig-

gers an internal memory program cycle only if the

STOP condition is internally decoded immediately

after the ACK bit; any STOP condition decoded

ternal programming cycle. All inputs are disabled

until the completion of this cycle and the Memory

will not respond to any request.

Minimizing System Delays by Polling On ACK

During the internal write cycle, the memory discon-

nects itself from the bus, and copies the data from

its internal latches to the memory cells. The maxi-