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SMC032AF 数据表(PDF) 29 Page - Numonyx B.V |
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SMC032AF 数据表(HTML) 29 Page - Numonyx B.V |
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29 / 82 page ![]() SMCxxxAF Command interface 29/82 Table 22. True IDE mode I/O Read/Write timing diagram Symbol Parameter(1) Mode 0Mode 1Mode 2Mode 3Mode 4 Unit t0 (2) Cycle time (min) 600 383 240 180 120 ns t1 Address Valid to -IORD/-IOWR setup (min) 70 50 30 30 25 ns t2 (2) -IORD/-IOWR (min) 165 125 100 80 70 ns t2 (2) -IORD/-IOWR (min) register (8 bit) 290 290 290 80 70 ns t2i (2) -IORD/-IOWR recovery time (min) - - - 70 25 ns t3 -IOWR data setup (min) 60 45 30 30 20 ns t4 -IOWR data hold (min) 30 20 15 10 10 ns t5 -IORD data setup (min) 50 35 20 20 20 ns t6 -IORD data hold (min) 5 5 5 5 5 ns t6Z (3) -IORD data tri-state (max) 30 30 30 30 30 ns t7 (4) Address valid to -IOCS16 assertion (max) 90 50 40 N/A N/A ns t8 (4) Address valid to -IOCS16 released (max) 60 45 30 N/A N/A ns t9 -IORD/-IOWR to address valid hold 20 15 10 10 10 ns 1. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF total load. 2. t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, t2, and t2i have to be met. The minimum total cycle time requirement is greater than the sum of t2 and t2i. This means a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the device's identify drive data. A CompactFlash memory card implementation should support any legal host implementation. 3. This parameter specifies the time from the falling edge of -IORD to the moment when the data bus is no longer driven by the CompactFlash memory card (tri-state). 4. t7 and t8 apply only to modes 0, 1 and 2. This signal is not valid for other modes. |
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