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数据搜索系统，热门电子元器件搜索 |
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SMC032AF 数据表(PDF) 32 Page - Numonyx B.V |
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SMC032AF 数据表(HTML) 32 Page - Numonyx B.V |
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32 / 82 page  Card configuration SMCxxxAF 32/82 6.2 Card Configuration and Status register (base + 02h in attribute memory) The Card Configuration and Status register contains information about the card’s status (see Table 27). 6.2.1 Changed Indicates that one or both of the pin replacement register (CRDY, or CWProt) bits are set to ‘1’. When the Changed bit is set, –STSCHG (pin 46) is held Low and if the SigChg bit is ‘1’ the card is configured for the I/O interface. 6.2.2 SigChg This bit is set and reset by the host to enable and disable a state-change signal from the Status register (issued on Status Changed pin 46). If no state change signal is desired, this bit should be set ‘0’ and pin 46 (–STSCHG) will be held High while the card is configured for I/O. 6.2.3 IOis8 The host sets this bit to ‘1’ if the card is to be configured in 8 bit I/O mode. The card is always configured for both 8 and 16 bit I/O, so this bit is ignored. 6.2.4 PwrDwn This bit indicates whether the card is in the power saving mode or active mode. When the PwrDwn bit is set to ‘1’, the card enters power-down mode. When set to ‘0’, the card enters active mode. The READY value on Pin Replacement register becomes BUSY when this bit is changed. READY will not become Ready until the power state requested has been entered. The card automatically powers down when it is idle and powers back up when it receives a command. 6.2.5 Int This bit represents the internal state of the interrupt request. It is available whether or not the I/O interface has been configured. It remains valid until the condition which caused the interrupt request has been serviced. If interrupts are disabled by the –IEN bit in the Device Control register, this bit is ‘0’. Table 27. Card Configuration and Status register (default value: 00h) Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Changed SigChg IOIS8 0 0 PwrDwn Int 0 Write 0 SigChg IOIS8 0 0 PwrDwn 0 0 |
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