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SN75DP129RHHTG4 数据表(PDF) 10 Page - Texas Instruments |
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SN75DP129RHHTG4 数据表(HTML) 10 Page - Texas Instruments |
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10 / 28 page  www.ti.com ELECTRICAL CHARACTERISTICS SWITCHING CHARACTERISTICS PULSE GENERATOR D.U.T. RT VOUT VCC 3.3V R =2k L W C =100pF L VIN SN75DP129 SLAS583A – JANUARY 2008 – REVISED MARCH 2008 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IL Low input current VCC = 3.6 V, VI = 0 V –10 10 µA Ilkg(AUX) Input leakage current AUX_I2C pins VCC = 3.6 V, VI = 3.6 V –10 10 µA CIO(AUX) Input/output capacitance AUX_I2C pins DC bias = 1.65 V, AC = 2.1 Vp-p, f = 100 kHz 15 pF VIH(AUX) High-level input voltage AUX_I2C pins 1.6 5.5 V VIL(AUX) Low-level input voltage AUX_I2C pins –0.2 0.4 V VOL(AUX) Low-level output voltage AUX_I2C pins IO = 4 mA 0.5 0.6 V Ilkg(I2C) Input leakage current I2C SDA/SCL pins VCC = 3.6 V, VI = 4.95 V –10 10 µA CIO(I2C) Input/output capacitance I2C SDA/SCL pins DC bias = 2.5 V, AC = 3.5 Vp-p, f = 100 kHz 15 pF VIH(I2C) High-level input voltage I2C SDA/SCL pins 2.1 5.5 V VIL(I2C) Low-level input voltage I2C SDA/SCL pins –0.2 1.5 V VOL(I2C) Low-level output voltage I2C SDA/SCL pins IO = 4 mA 0.2 V over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH1 Propagation delay time, low to high Source to Sink 204 459 ns tPHL1 Propagation delay time, high to low Source to Sink 35 200 ns tPLH2 Propagation delay time, low to high Sink to Source 80 251 ns tPHL2 Propagation delay time, high to low Sink to Source 35 200 ns tf1 Output signal fall time Sink Side 20 72 ns tf2 Output signal fall time Source Side 20 72 ns fSCL SCL clock frequency for internal register Source Side 100 kHz tW(L) Clock LOW period for I2C register Source Side 4.7 µs tW(H) Clock HIGH period for internal register Source Side 4.0 µs tSU1 Internal register setup time, SDA to SCL Source Side 250 ns th(1) Internal register hold time, SCL to SDA Source Side 0 µs t(buf) Internal register bus free time between STOP and START Source Side 4.7 µs tsu(2) Internal register setup time, SCL to START Source Side 4.7 µs th(2) Internal register hold time, START to SCL Source Side 4.0 µs tsu(3) Internal register hold time, SCL to STOP Source Side 4.0 µs Figure 8. Source Side Test Circuit (AUX_I2C) 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP129 |
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